1  /* PR inline-asm/20314 */
       2  /* { dg-do compile { target { { i?86-*-* x86_64-*-* } && { ! { ia32 } } } } } */
       3  /* { dg-do compile { target ia64-*-* powerpc*-*-* } } */
       4  
       5  int a, b, c, d, e, f, g, h, i, j, k, l;
       6  
       7  void
       8  f1 (void)
       9  {
      10    __asm__ volatile (""
      11  		    : [a] "+r" (a), [b] "+r" (b), [c] "+r" (c), [d] "+r" (d),
      12  		      [e] "+r" (e), [f] "+r" (f), [g] "+r" (g), [h] "+r" (h),
      13  		      [i] "+r" (i), [j] "+r" (j), [k] "+r" (k), [l] "+r" (l));
      14  }
      15  
      16  void
      17  f2 (void)
      18  {
      19    __asm__ volatile (""
      20  		    : [a] "+r,m" (a), [b] "+r,m" (b), [c] "+r,m" (c), [d] "+r,m" (d),
      21  		      [e] "+r,m" (e), [f] "+r,m" (f), [g] "+r,m" (g), [h] "+r,m" (h),
      22  		      [i] "+r,m" (i), [j] "+r,m" (j), [k] "+r,m" (k), [l] "+r,m" (l));
      23  }
      24  
      25  void
      26  f3 (void)
      27  {
      28    __asm__ volatile (""
      29  		    : [a] "=r" (a), [b] "=r" (b), [c] "=r" (c), [d] "=r" (d),
      30  		      [e] "=r" (e), [f] "=r" (f), [g] "=r" (g), [h] "=r" (h),
      31  		      [i] "=r" (i), [j] "=r" (j), [k] "=r" (k), [l] "=r" (l)
      32  		    : "[a]" (a), "[b]" (b), "[c]" (c), "[d]" (d),
      33  		      "[e]" (e), "[f]" (f), "[g]" (g), "[h]" (h),
      34  		      "[i]" (i), "[j]" (j), "[k]" (k), "[l]" (l));
      35  }
      36  
      37  void
      38  f4 (void)
      39  {
      40    __asm__ volatile (""
      41  		    : [a] "=r,m" (a), [b] "=r,m" (b), [c] "=r,m" (c), [d] "=r,m" (d),
      42  		      [e] "=r,m" (e), [f] "=r,m" (f), [g] "=r,m" (g), [h] "=r,m" (h),
      43  		      [i] "=r,m" (i), [j] "=r,m" (j), [k] "=r,m" (k), [l] "=r,m" (l)
      44  		    : "[a],m" (a), "[b],m" (b), "[c],m" (c), "[d],m" (d),
      45  		      "[e],m" (e), "[f],m" (f), "[g],m" (g), "[h],m" (h),
      46  		      "[i],m" (i), "[j],m" (j), "[k],m" (k), "[l],m" (l));
      47  }