1  /* { dg-do compile { target aarch64-*-* } } */
       2  /* { dg-options "-mtune=cortex-a53 -fdump-rtl-combine -O2" } */
       3  
       4  /* Taken from
       5       gcc/testsuite/gcc.dg/asr_div1.c -O2 -fdump-rtl-all -mtune=cortex-a53
       6     for aarch64, hand editing to the new format.  */
       7  
       8  int __RTL (startwith ("combine")) f1 (int n)
       9  {
      10  (function "f1"
      11    (param "n"
      12      (DECL_RTL (reg/v:SI <1> [ n ]))
      13      (DECL_RTL_INCOMING (reg:SI x0 [ n ]))
      14    ) ;; param "n"
      15    (insn-chain
      16      (block 2
      17        (edge-from entry (flags "FALLTHRU"))
      18        (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
      19        (cinsn 8 (set (reg:DI <2>)
      20          (lshiftrt:DI (reg:DI <0>)
      21              (const_int 32)))
      22          "../../src/gcc/testsuite/gcc.dg/asr_div1.c":14
      23          (expr_list:REG_DEAD (reg:DI <0>)))
      24        (cinsn 9 (set (reg:SI <1>)
      25          (ashiftrt:SI (subreg:SI (reg:DI <2>) 0)
      26              (const_int 3)))
      27          "../../src/gcc/testsuite/gcc.dg/asr_div1.c":14
      28          (expr_list:REG_DEAD (reg:DI <2>)))
      29  
      30        ;; Extra insn, to avoid all of the above from being deleted by DCE
      31        (insn 10 (use (reg/i:SI <1>)))
      32  
      33        (edge-to exit (flags "FALLTHRU"))
      34      ) ;; block 2
      35    ) ;; insn-chain
      36  ) ;; function
      37  }
      38  
      39  /* Verify that insns 8 and 9 get combined into a shift of 35 (0x23) */
      40  /* { dg-final { scan-rtl-dump "allowing combination of insns 8 and 9" "combine" } } */
      41  /* { dg-final { scan-rtl-dump "modifying insn i3     9: r\[0-9\]+:SI#0=r\[0-9\]+:DI>>0x23" "combine" } } */