1  /* PR debug/51557 */
       2  /* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
       3  /* { dg-options "-Os -fno-asynchronous-unwind-tables -g -fsel-sched-pipelining -fselective-scheduling2" } */
       4  
       5  extern int baz (void);
       6  extern void bar (int, int, int, int, int, int, int);
       7  
       8  void
       9  synth (int *values, int n_values, int ci, int s1, int v, int s2)
      10  {
      11    while (--s1)
      12      {
      13        int r1 = values[s1];
      14        int co = ci ? r1 : baz () < r1;
      15        bar (0, n_values, s1, s2, v, co, 0);
      16      }
      17  }