1 /* Based on execute/simd-1.c, modified by joern.rennecke@st.com to
2 trigger a reload bug. Verified for gcc mainline from 20050722 13:00 UTC
3 for sh-elf -m4 -O2. */
4 /* { dg-options "-Wno-psabi -fwrapv" } */
5 /* { dg-add-options stack_size } */
6
7 #ifndef STACK_SIZE
8 #define STACK_SIZE (256*1024)
9 #endif
10
11 extern void abort (void);
12 extern void exit (int);
13
14 typedef struct { char c[STACK_SIZE/2]; } big_t;
15
16 typedef int __attribute__((mode(SI))) __attribute__((vector_size (8))) vecint;
17 typedef int __attribute__((mode(SI))) siint;
18
19 vecint i = { 150, 100 };
20 vecint j = { 10, 13 };
21 vecint k;
22
23 union {
24 vecint v;
25 siint i[2];
26 } res;
27
28 void
29 verify (siint a1, siint a2, siint b1, siint b2, big_t big)
30 {
31 if (a1 != b1
32 || a2 != b2)
33 abort ();
34 }
35
36 int
37 main ()
38 {
39 big_t big;
40 vecint k0, k1, k2, k3, k4, k5, k6, k7;
41
42 k0 = i + j;
43 res.v = k0;
44
45 verify (res.i[0], res.i[1], 160, 113, big);
46
47 k1 = i * j;
48 res.v = k1;
49
50 verify (res.i[0], res.i[1], 1500, 1300, big);
51
52 k2 = i / j;
53 /* This is the observed failure - reload 0 has the wrong type and thus the
54 conflict with reload 1 is missed:
55
56 (insn:HI 94 92 96 1 pr23135.c:46 (parallel [
57 (set (subreg:SI (reg:DI 253) 0)
58 (div:SI (reg:SI 4 r4)
59 (reg:SI 5 r5)))
60 (clobber (reg:SI 146 pr))
61 (clobber (reg:DF 64 fr0))
62 (clobber (reg:DF 66 fr2))
63 (use (reg:PSI 151 ))
64 (use (reg/f:SI 256))
65 ]) 60 {divsi3_i4} (insn_list:REG_DEP_TRUE 90 (insn_list:REG_DEP_TRUE 89
66 (insn_list:REG_DEP_TRUE 42 (insn_list:REG_DEP_TRUE 83 (insn_list:REG_DEP_TRUE 92
67 (insn_list:REG_DEP_TRUE 91 (nil)))))))
68 (expr_list:REG_DEAD (reg:SI 4 r4)
69 (expr_list:REG_DEAD (reg:SI 5 r5)
70 (expr_list:REG_UNUSED (reg:DF 66 fr2)
71 (expr_list:REG_UNUSED (reg:DF 64 fr0)
72 (expr_list:REG_UNUSED (reg:SI 146 pr)
73 (insn_list:REG_RETVAL 91 (nil))))))))
74
75 Reloads for insn # 94
76 Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 14 r14)
77 (const_int 64 [0x40]))
78 GENERAL_REGS, RELOAD_FOR_OUTADDR_ADDRESS (opnum = 0)
79 reload_in_reg: (plus:SI (reg/f:SI 14 r14)
80 (const_int 64 [0x40]))
81 reload_reg_rtx: (reg:SI 3 r3)
82 Reload 1: GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, se
83 condary_reload_p
84 reload_reg_rtx: (reg:SI 3 r3)
85 Reload 2: reload_out (SI) = (mem:SI (plus:SI (plus:SI (reg/f:SI 14 r14)
86 (const_int 64 [0x40]))
87 (const_int 28 [0x1c])) [ 16 S8 A32])
88 FPUL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
89 reload_out_reg: (subreg:SI (reg:DI 253) 0)
90 reload_reg_rtx: (reg:SI 150 fpul)
91 secondary_out_reload = 1
92
93 Reload 3: reload_in (SI) = (symbol_ref:SI ("__sdivsi3_i4") [flags 0x1])
94 GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
95 reload_in_reg: (reg/f:SI 256)
96 reload_reg_rtx: (reg:SI 3 r3)
97 */
98
99
100 res.v = k2;
101
102 verify (res.i[0], res.i[1], 15, 7, big);
103
104 k3 = i & j;
105 res.v = k3;
106
107 verify (res.i[0], res.i[1], 2, 4, big);
108
109 k4 = i | j;
110 res.v = k4;
111
112 verify (res.i[0], res.i[1], 158, 109, big);
113
114 k5 = i ^ j;
115 res.v = k5;
116
117 verify (res.i[0], res.i[1], 156, 105, big);
118
119 k6 = -i;
120 res.v = k6;
121 verify (res.i[0], res.i[1], -150, -100, big);
122
123 k7 = ~i;
124 res.v = k7;
125 verify (res.i[0], res.i[1], -151, -101, big);
126
127 k = k0 + k1 + k3 + k4 + k5 + k6 + k7;
128 res.v = k;
129 verify (res.i[0], res.i[1], 1675, 1430, big);
130
131 k = k0 * k1 * k3 * k4 * k5 * k6 * k7;
132 res.v = k;
133 verify (res.i[0], res.i[1], 1456467968, -1579586240, big);
134
135 k = k0 / k1 / k2 / k3 / k4 / k5 / k6 / k7;
136 res.v = k;
137 verify (res.i[0], res.i[1], 0, 0, big);
138
139 exit (0);
140 }