1  /* { dg-do compile { target aarch64-*-* } } */
       2  /* { dg-additional-options "-march=armv8.6-a+sve -fsanitize-address-use-after-scope" } */
       3  
       4  #include <arm_sve.h>
       5  
       6  __attribute__((noinline, noclone)) int
       7  foo (char *a)
       8  {
       9    int i, j = 0;
      10    asm volatile ("" : "+r" (a) : : "memory");
      11    for (i = 0; i < 12; i++)
      12      j += a[i];
      13    return j;
      14  }
      15  
      16  int
      17  main ()
      18  {
      19    int i, j = 0;
      20    for (i = 0; i < 4; i++)
      21      {
      22        char a[12];
      23        __SVInt8_t freq;
      24        /* Just do something with that `freq` variable so that the compiler
      25  	 doesn't optimise its use away.  */
      26        if (__builtin_bcmp (&freq, a, 10))
      27  	j += 1;
      28        __builtin_memset (a, 0, sizeof (a));
      29        j += foo (a);
      30      }
      31    return j;
      32  }
      33  
      34  /* Just ensure this compiles without giving an ICE.
      35     This is the equivalent of PR 97696 but for HWASAN.  HWASAN can handle
      36     poly_int sized variables, and this testcase ensures that we don't ICE when
      37     given them.  */