1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright (C) 2001-2023 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 /* Get Xtensa configuration settings */
22 #include "xtensa-dynconfig.h"
23
24 /* External variables defined in xtensa.cc. */
25
26 /* Macros used in the machine description to select various Xtensa
27 configuration options. */
28 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
29 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
30 #define TARGET_MAC16 XCHAL_HAVE_MAC16
31 #define TARGET_MUL16 XCHAL_HAVE_MUL16
32 #define TARGET_MUL32 XCHAL_HAVE_MUL32
33 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
34 #define TARGET_DIV32 XCHAL_HAVE_DIV32
35 #define TARGET_NSA XCHAL_HAVE_NSA
36 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
37 #define TARGET_SEXT XCHAL_HAVE_SEXT
38 #define TARGET_CLAMPS XCHAL_HAVE_CLAMPS
39 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
40 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
41 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
42 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
43 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
44 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
45 #define TARGET_HARD_FLOAT_POSTINC XCHAL_HAVE_FP_POSTINC
46 #define TARGET_ABS XCHAL_HAVE_ABS
47 #define TARGET_ADDX XCHAL_HAVE_ADDX
48 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
49 #define TARGET_S32C1I XCHAL_HAVE_S32C1I
50 #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS
51 #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR
52 #define TARGET_LOOPS XCHAL_HAVE_LOOPS
53 #define TARGET_WINDOWED_ABI_DEFAULT (XSHAL_ABI == XTHAL_ABI_WINDOWED)
54 #define TARGET_WINDOWED_ABI xtensa_windowed_abi
55 #define TARGET_DEBUG XCHAL_HAVE_DEBUG
56 #define TARGET_L32R XCHAL_HAVE_L32R
57
58 #define TARGET_DEFAULT (MASK_SERIALIZE_VOLATILE)
59
60 #ifndef HAVE_AS_TLS
61 #define HAVE_AS_TLS 0
62 #endif
63
64 /* Define this if the target has no hardware divide instructions. */
65 #if !__XCHAL_HAVE_DIV32
66 #define TARGET_HAS_NO_HW_DIVIDE
67 #endif
68
69
70 /* Target CPU builtins. */
71 #define TARGET_CPU_CPP_BUILTINS() \
72 do { \
73 const char **builtin; \
74 builtin_assert ("cpu=xtensa"); \
75 builtin_assert ("machine=xtensa"); \
76 builtin_define ("__xtensa__"); \
77 builtin_define ("__XTENSA__"); \
78 builtin_define (TARGET_WINDOWED_ABI ? \
79 "__XTENSA_WINDOWED_ABI__" : "__XTENSA_CALL0_ABI__");\
80 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
81 if (!TARGET_HARD_FLOAT) \
82 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
83 for (builtin = xtensa_get_config_strings (); *builtin; ++builtin) \
84 builtin_define (*builtin); \
85 } while (0)
86
87 #define CPP_SPEC " %(subtarget_cpp_spec) "
88
89 #ifndef SUBTARGET_CPP_SPEC
90 #define SUBTARGET_CPP_SPEC ""
91 #endif
92
93 #define EXTRA_SPECS \
94 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
95
96 /* Target machine storage layout */
97
98 /* Define this if most significant bit is lowest numbered
99 in instructions that operate on numbered bit-fields. */
100 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
101
102 /* Define this if most significant byte of a word is the lowest numbered. */
103 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
104
105 /* Define this if most significant word of a multiword number is the lowest. */
106 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
107
108 #define MAX_BITS_PER_WORD 32
109
110 /* Width of a word, in units (bytes). */
111 #define UNITS_PER_WORD 4
112 #define MIN_UNITS_PER_WORD 4
113
114 /* Width of a floating point register. */
115 #define UNITS_PER_FPREG 4
116
117 /* Size in bits of various types on the target machine. */
118 #define INT_TYPE_SIZE 32
119 #define SHORT_TYPE_SIZE 16
120 #define LONG_TYPE_SIZE 32
121 #define LONG_LONG_TYPE_SIZE 64
122 #define FLOAT_TYPE_SIZE 32
123 #define DOUBLE_TYPE_SIZE 64
124 #define LONG_DOUBLE_TYPE_SIZE 64
125
126 /* Allocation boundary (in *bits*) for storing pointers in memory. */
127 #define POINTER_BOUNDARY 32
128
129 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
130 #define PARM_BOUNDARY 32
131
132 /* Allocation boundary (in *bits*) for the code of a function. */
133 #define FUNCTION_BOUNDARY 32
134
135 /* Alignment of field after 'int : 0' in a structure. */
136 #define EMPTY_FIELD_BOUNDARY 32
137
138 /* Every structure's size must be a multiple of this. */
139 #define STRUCTURE_SIZE_BOUNDARY 8
140
141 /* There is no point aligning anything to a rounder boundary than this. */
142 #define BIGGEST_ALIGNMENT 128
143
144 /* Set this nonzero if move instructions will actually fail to work
145 when given unaligned data. */
146 #define STRICT_ALIGNMENT 1
147
148 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
149 for QImode, because there is no 8-bit load from memory with sign
150 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
151 loads both with and without sign extension. */
152 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
153 do { \
154 if (GET_MODE_CLASS (MODE) == MODE_INT \
155 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
156 { \
157 if ((MODE) == QImode) \
158 (UNSIGNEDP) = 1; \
159 (MODE) = SImode; \
160 } \
161 } while (0)
162
163 /* Imitate the way many other C compilers handle alignment of
164 bitfields and the structures that contain them. */
165 #define PCC_BITFIELD_TYPE_MATTERS 1
166
167 /* Align arrays, unions and records to at least a word boundary.
168 One use of this macro is to increase alignment of medium-size
169 data to make it all fit in fewer cache lines. Another is to
170 cause character arrays to be word-aligned so that 'strcpy' calls
171 that copy constants to character arrays can be done inline. */
172 #undef DATA_ALIGNMENT
173 #define DATA_ALIGNMENT(TYPE, ALIGN) \
174 (!optimize_size && (((ALIGN) < BITS_PER_WORD) \
175 && (TREE_CODE (TYPE) == ARRAY_TYPE \
176 || TREE_CODE (TYPE) == UNION_TYPE \
177 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
178
179 /* Operations between registers always perform the operation
180 on the full register even if a narrower mode is specified. */
181 #define WORD_REGISTER_OPERATIONS 1
182
183 /* Xtensa loads are zero-extended by default. */
184 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
185
186 /* Standard register usage. */
187
188 /* Number of actual hardware registers.
189 The hardware registers are assigned numbers for the compiler
190 from 0 to just below FIRST_PSEUDO_REGISTER.
191 All registers that the compiler knows about must be given numbers,
192 even those that are not normally considered general registers.
193
194 The fake frame pointer and argument pointer will never appear in
195 the generated code, since they will always be eliminated and replaced
196 by either the stack pointer or the hard frame pointer.
197
198 0 - 15 AR[0] - AR[15]
199 16 FRAME_POINTER (fake = initial sp)
200 17 ARG_POINTER (fake = initial sp + framesize)
201 18 BR[0] for floating-point CC
202 19 - 34 FR[0] - FR[15]
203 35 MAC16 accumulator */
204
205 #define FIRST_PSEUDO_REGISTER 36
206
207 /* Return the stabs register number to use for REGNO. */
208 #define DEBUGGER_REGNO(REGNO) xtensa_debugger_regno (REGNO)
209
210 /* 1 for registers that have pervasive standard uses
211 and are not available for the register allocator. */
212 #define FIXED_REGISTERS \
213 { \
214 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
215 1, 1, 0, \
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
217 0, \
218 }
219
220 /* 1 for registers not available across function calls.
221 These need not include the FIXED_REGISTERS but must any
222 registers that can be used without being saved.
223 The latter must include the registers where values are returned
224 and the register where structure-value addresses are passed.
225 Aside from that, you can include as many other registers as you like.
226
227 The value encoding is the following:
228 1: register is used by all ABIs;
229 bit 1 is set: register is used by windowed ABI;
230 bit 2 is set: register is used by call0 ABI.
231
232 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
233
234 #define CALL_REALLY_USED_REGISTERS \
235 { \
236 1, 0, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \
237 0, 0, 1, \
238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
239 1, \
240 }
241
242 /* For the windowed register ABI on Xtensa processors, the allocation
243 order is as specified below by REG_ALLOC_ORDER.
244 For the call0 ABI, on the other hand, ADJUST_REG_ALLOC_ORDER hook
245 will be called once at the start of IRA, replacing it with the
246 appropriate one. */
247
248 #define REG_ALLOC_ORDER \
249 { \
250 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
251 18, \
252 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
253 0, 1, 16, 17, \
254 35, \
255 }
256 #define ADJUST_REG_ALLOC_ORDER xtensa_adjust_reg_alloc_order ()
257
258 /* Internal macros to classify a register number. */
259
260 /* 16 address registers + fake registers */
261 #define GP_REG_FIRST 0
262 #define GP_REG_LAST 17
263 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
264
265 /* Coprocessor registers */
266 #define BR_REG_FIRST 18
267 #define BR_REG_LAST 18
268 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
269
270 /* 16 floating-point registers */
271 #define FP_REG_FIRST 19
272 #define FP_REG_LAST 34
273 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
274
275 /* MAC16 accumulator */
276 #define ACC_REG_FIRST 35
277 #define ACC_REG_LAST 35
278 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
279
280 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
281 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
282 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
283 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
284
285 /* Register to use for pushing function arguments. */
286 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
287
288 /* Base register for access to local variables of the function. */
289 #define HARD_FRAME_POINTER_REGNUM \
290 (TARGET_WINDOWED_ABI \
291 ? XTENSA_WINDOWED_HARD_FRAME_POINTER_REGNUM \
292 : XTENSA_CALL0_HARD_FRAME_POINTER_REGNUM)
293
294 #define XTENSA_WINDOWED_HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
295 #define XTENSA_CALL0_HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 15)
296
297 /* The register number of the frame pointer register, which is used to
298 access automatic variables in the stack frame. For Xtensa, this
299 register never appears in the output. It is always eliminated to
300 either the stack pointer or the hard frame pointer. */
301 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
302
303 /* Base register for access to arguments of the function. */
304 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
305
306 /* Hard frame pointer is neither frame nor arg pointer.
307 The definitions are here because actual hard frame pointer register
308 definition is not a preprocessor constant. */
309 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
310 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
311
312 /* For now we don't try to use the full set of boolean registers. Without
313 software pipelining of FP operations, there's not much to gain and it's
314 a real pain to get them reloaded. */
315 #define FPCC_REGNUM (BR_REG_FIRST + 0)
316
317 /* It is as good or better to call a constant function address than to
318 call an address kept in a register. */
319 #define NO_FUNCTION_CSE 1
320
321 /* Xtensa processors have "register windows". GCC does not currently
322 take advantage of the possibility for variable-sized windows; instead,
323 we use a fixed window size of 8. */
324
325 #define INCOMING_REGNO(OUT) \
326 (TARGET_WINDOWED_ABI ? \
327 ((GP_REG_P (OUT) && \
328 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
329 (OUT) - WINDOW_SIZE : (OUT)) : (OUT))
330
331 #define OUTGOING_REGNO(IN) \
332 (TARGET_WINDOWED_ABI ? \
333 ((GP_REG_P (IN) && \
334 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
335 (IN) + WINDOW_SIZE : (IN)) : (IN))
336
337
338 /* Define the classes of registers for register constraints in the
339 machine description. */
340 enum reg_class
341 {
342 NO_REGS, /* no registers in set */
343 BR_REGS, /* coprocessor boolean registers */
344 FP_REGS, /* floating point registers */
345 ACC_REG, /* MAC16 accumulator */
346 SP_REG, /* sp register (aka a1) */
347 ISC_REGS, /* registers for indirect sibling calls */
348 RL_REGS, /* preferred reload regs (not sp or fp) */
349 GR_REGS, /* integer registers except sp */
350 AR_REGS, /* all integer registers */
351 ALL_REGS, /* all registers */
352 LIM_REG_CLASSES /* max value + 1 */
353 };
354
355 #define N_REG_CLASSES (int) LIM_REG_CLASSES
356
357 #define GENERAL_REGS AR_REGS
358
359 /* An initializer containing the names of the register classes as C
360 string constants. These names are used in writing some of the
361 debugging dumps. */
362 #define REG_CLASS_NAMES \
363 { \
364 "NO_REGS", \
365 "BR_REGS", \
366 "FP_REGS", \
367 "ACC_REG", \
368 "SP_REG", \
369 "ISC_REGS", \
370 "RL_REGS", \
371 "GR_REGS", \
372 "AR_REGS", \
373 "ALL_REGS" \
374 }
375
376 /* Contents of the register classes. The Nth integer specifies the
377 contents of class N. The way the integer MASK is interpreted is
378 that register R is in the class if 'MASK & (1 << R)' is 1. */
379 #define REG_CLASS_CONTENTS \
380 { \
381 { 0x00000000, 0x00000000 }, /* no registers */ \
382 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
383 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
384 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
385 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
386 { 0x000001fc, 0x00000000 }, /* registers for indirect sibling calls */ \
387 { 0x0000fffd, 0x00000000 }, /* preferred reload registers */ \
388 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
389 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
390 { 0xffffffff, 0x0000000f } /* all registers */ \
391 }
392
393 /* A C expression whose value is a register class containing hard
394 register REGNO. In general there is more that one such class;
395 choose a class which is "minimal", meaning that no smaller class
396 also contains the register. */
397 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class (REGNO)
398
399 /* Use the Xtensa AR register file for base registers.
400 No index registers. */
401 #define BASE_REG_CLASS AR_REGS
402 #define INDEX_REG_CLASS NO_REGS
403
404 /* The small_register_classes_for_mode_p hook must always return true for
405 Xtrnase, because all of the 16 AR registers may be explicitly used in
406 the RTL, as either incoming or outgoing arguments. */
407 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
408
409 /* Stack layout; function entry, exit and calling. */
410
411 #define STACK_GROWS_DOWNWARD 1
412
413 #define FRAME_GROWS_DOWNWARD (flag_stack_protect \
414 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
415
416 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
417 they are eliminated to either the stack pointer or hard frame pointer.
418 Since hard frame pointer is different register in windowed and call0
419 ABIs list them both and only allow real HARD_FRAME_POINTER_REGNUM in
420 TARGET_CAN_ELIMINATE. */
421 #define ELIMINABLE_REGS \
422 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
423 { ARG_POINTER_REGNUM, XTENSA_WINDOWED_HARD_FRAME_POINTER_REGNUM}, \
424 { ARG_POINTER_REGNUM, XTENSA_CALL0_HARD_FRAME_POINTER_REGNUM}, \
425 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
426 { FRAME_POINTER_REGNUM, XTENSA_WINDOWED_HARD_FRAME_POINTER_REGNUM}, \
427 { FRAME_POINTER_REGNUM, XTENSA_CALL0_HARD_FRAME_POINTER_REGNUM}}
428
429 /* Specify the initial difference between the specified pair of registers. */
430 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
431 (OFFSET) = xtensa_initial_elimination_offset ((FROM), (TO))
432
433 /* If defined, the maximum amount of space required for outgoing
434 arguments will be computed and placed into the variable
435 'crtl->outgoing_args_size'. No space will be pushed
436 onto the stack for each call; instead, the function prologue
437 should increase the stack frame size by this amount. */
438 #define ACCUMULATE_OUTGOING_ARGS 1
439
440 /* Offset from the argument pointer register to the first argument's
441 address. On some machines it may depend on the data type of the
442 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
443 location above the first argument's address. */
444 #define FIRST_PARM_OFFSET(FNDECL) 0
445
446 /* Align stack frames on 128 bits for Xtensa. This is necessary for
447 128-bit datatypes defined in TIE (e.g., for Vectra). */
448 #define STACK_BOUNDARY 128
449
450 /* Use a fixed register window size of 8. */
451 #define WINDOW_SIZE (TARGET_WINDOWED_ABI ? 8 : 0)
452
453 /* Symbolic macros for the registers used to return integer, floating
454 point, and values of coprocessor and user-defined modes. */
455 #define GP_RETURN_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
456 #define GP_RETURN_LAST (GP_RETURN_FIRST + 3)
457 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
458
459 /* Symbolic macros for the first/last argument registers. */
460 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
461 #define GP_ARG_LAST (GP_REG_FIRST + 7)
462 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
463 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
464
465 #define MAX_ARGS_IN_REGISTERS 6
466
467 /* Don't worry about compatibility with PCC. */
468 #define DEFAULT_PCC_STRUCT_RETURN 0
469
470 /* A C expression that is nonzero if REGNO is the number of a hard
471 register in which function arguments are sometimes passed. This
472 does *not* include implicit arguments such as the static chain and
473 the structure-value address. On many machines, no registers can be
474 used for this purpose since all function arguments are pushed on
475 the stack. */
476 #define FUNCTION_ARG_REGNO_P(N) \
477 IN_RANGE ((N), GP_OUTGOING_ARG_FIRST, GP_OUTGOING_ARG_LAST)
478
479 /* Record the number of argument words seen so far, along with a flag to
480 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
481 is used for both incoming and outgoing args, so a separate flag is
482 needed. */
483 typedef struct xtensa_args
484 {
485 int arg_words;
486 int incoming;
487 } CUMULATIVE_ARGS;
488
489 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
490 init_cumulative_args (&CUM, 0)
491
492 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
493 init_cumulative_args (&CUM, 1)
494
495 /* Profiling Xtensa code is typically done with the built-in profiling
496 feature of Tensilica's instruction set simulator, which does not
497 require any compiler support. Profiling code on a real (i.e.,
498 non-simulated) Xtensa processor is currently only supported by
499 GNU/Linux with glibc. The glibc version of _mcount doesn't require
500 counter variables. The _mcount function needs the current PC and
501 the current return address to identify an arc in the call graph.
502 Pass the current return address as the first argument; the current
503 PC is available as a0 in _mcount's register window. Both of these
504 values contain window size information in the two most significant
505 bits; we assume that _mcount will mask off those bits. The call to
506 _mcount uses a window size of 8 to make sure that it doesn't clobber
507 any incoming argument values. */
508
509 #define NO_PROFILE_COUNTERS 1
510
511 #define FUNCTION_PROFILER(FILE, LABELNO) \
512 do { \
513 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
514 if (flag_pic) \
515 { \
516 fprintf (FILE, "\tmovi\ta%d, _mcount@PLT\n", WINDOW_SIZE); \
517 fprintf (FILE, "\tcallx%d\ta%d\n", WINDOW_SIZE, WINDOW_SIZE); \
518 } \
519 else \
520 fprintf (FILE, "\tcall%d\t_mcount\n", WINDOW_SIZE); \
521 } while (0)
522
523 /* Stack pointer value doesn't matter at exit. */
524 #define EXIT_IGNORE_STACK 1
525
526 /* Size in bytes of the trampoline, as an integer. Make sure this is
527 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
528 #define TRAMPOLINE_SIZE (TARGET_WINDOWED_ABI ? \
529 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \
530 60 : 52) : \
531 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \
532 32 : 24))
533
534 /* Alignment required for trampolines, in bits. */
535 #define TRAMPOLINE_ALIGNMENT 32
536
537 /* If defined, a C expression that produces the machine-specific code
538 to setup the stack so that arbitrary frames can be accessed.
539
540 On Xtensa, a stack back-trace must always begin from the stack pointer,
541 so that the register overflow save area can be located. However, the
542 stack-walking code in GCC always begins from the hard_frame_pointer
543 register, not the stack pointer. The frame pointer is usually equal
544 to the stack pointer, but the __builtin_return_address and
545 __builtin_frame_address functions will not work if count > 0 and
546 they are called from a routine that uses alloca. These functions
547 are not guaranteed to work at all if count > 0 so maybe that is OK.
548
549 A nicer solution would be to allow the architecture-specific files to
550 specify whether to start from the stack pointer or frame pointer. That
551 would also allow us to skip the machine->accesses_prev_frame stuff that
552 we currently need to ensure that there is a frame pointer when these
553 builtin functions are used. */
554
555 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
556
557 /* A C expression whose value is RTL representing the address in a
558 stack frame where the pointer to the caller's frame is stored.
559 Assume that FRAMEADDR is an RTL expression for the address of the
560 stack frame itself.
561
562 For Xtensa, there is no easy way to get the frame pointer if it is
563 not equivalent to the stack pointer. Moreover, the result of this
564 macro is used for continuing to walk back up the stack, so it must
565 return the stack pointer address. Thus, there is some inconsistency
566 here in that __builtin_frame_address will return the frame pointer
567 when count == 0 and the stack pointer when count > 0. */
568
569 #define DYNAMIC_CHAIN_ADDRESS(frame) \
570 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
571
572 /* Define this if the return address of a particular stack frame is
573 accessed from the frame pointer of the previous stack frame. */
574 #define RETURN_ADDR_IN_PREVIOUS_FRAME TARGET_WINDOWED_ABI
575
576 /* A C expression whose value is RTL representing the value of the
577 return address for the frame COUNT steps up from the current
578 frame, after the prologue. */
579 #define RETURN_ADDR_RTX xtensa_return_addr
580
581 /* Addressing modes, and classification of registers for them. */
582
583 /* C expressions which are nonzero if register number NUM is suitable
584 for use as a base or index register in operand addresses. */
585
586 #define REGNO_OK_FOR_INDEX_P(NUM) 0
587 #define REGNO_OK_FOR_BASE_P(NUM) \
588 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
589
590 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
591 valid for use as a base or index register. */
592
593 #define BASE_REG_P(X, STRICT) \
594 ((!(STRICT) && ! HARD_REGISTER_P (X)) \
595 || REGNO_OK_FOR_BASE_P (REGNO (X)))
596
597 /* Maximum number of registers that can appear in a valid memory address. */
598 #define MAX_REGS_PER_ADDRESS 1
599
600 /* A C expression that is 1 if the RTX X is a constant which is a
601 valid address. This is defined to be the same as 'CONSTANT_P (X)',
602 but rejecting CONST_DOUBLE. */
603 #define CONSTANT_ADDRESS_P(X) \
604 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
605 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
606 || (GET_CODE (X) == CONST)))
607
608 /* A C expression that is nonzero if X is a legitimate immediate
609 operand on the target machine when generating position independent
610 code. */
611 #define LEGITIMATE_PIC_OPERAND_P(X) \
612 ((GET_CODE (X) != SYMBOL_REF \
613 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
614 && GET_CODE (X) != LABEL_REF \
615 && GET_CODE (X) != CONST)
616
617 /* Specify the machine mode that this machine uses
618 for the index in the tablejump instruction. */
619 #define CASE_VECTOR_MODE (SImode)
620
621 /* Define this as 1 if 'char' should by default be signed; else as 0. */
622 #define DEFAULT_SIGNED_CHAR 0
623
624 /* Max number of bytes we can move from memory to memory
625 in one reasonably fast instruction. */
626 #define MOVE_MAX 4
627 #define MAX_MOVE_MAX 4
628
629 /* Prefer word-sized loads. */
630 #define SLOW_BYTE_ACCESS 1
631
632 /* Shift instructions ignore all but the low-order few bits. */
633 #define SHIFT_COUNT_TRUNCATED 1
634
635 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
636 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
637
638 /* Specify the machine mode that pointers have.
639 After generation of rtl, the compiler makes no further distinction
640 between pointers and any other objects of this machine mode. */
641 #define Pmode SImode
642
643 /* A function address in a call instruction is a word address (for
644 indexing purposes) so give the MEM rtx a words's mode. */
645 #define FUNCTION_MODE SImode
646
647 #define BRANCH_COST(speed_p, predictable_p) 3
648
649 /* How to refer to registers in assembler output.
650 This sequence is indexed by compiler's hard-register-number (see above). */
651 #define REGISTER_NAMES \
652 { \
653 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
654 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
655 "fp", "argp", "b0", \
656 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
657 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
658 "acc" \
659 }
660
661 /* If defined, a C initializer for an array of structures containing a
662 name and a register number. This macro defines additional names
663 for hard registers, thus allowing the 'asm' option in declarations
664 to refer to registers using alternate names. */
665 #define ADDITIONAL_REGISTER_NAMES \
666 { \
667 { "a1", 1 + GP_REG_FIRST } \
668 }
669
670 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
671 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
672
673 /* Globalizing directive for a label. */
674 #define GLOBAL_ASM_OP "\t.global\t"
675
676 /* Declare an uninitialized external linkage data object. */
677 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
678 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
679
680 /* This is how to output an element of a case-vector that is absolute. */
681 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
682 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
683 LOCAL_LABEL_PREFIX, VALUE)
684
685 /* This is how to output an element of a case-vector that is relative.
686 This is used for pc-relative code. */
687 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
688 do { \
689 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
690 LOCAL_LABEL_PREFIX, (VALUE), \
691 LOCAL_LABEL_PREFIX, (REL)); \
692 } while (0)
693
694 /* This is how to output an assembler line that says to advance the
695 location counter to a multiple of 2**LOG bytes. */
696 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
697 do { \
698 if ((LOG) != 0) \
699 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
700 } while (0)
701
702 /* Indicate that jump tables go in the text section. This is
703 necessary when compiling PIC code. */
704 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
705
706
707 /* Define the strings to put out for each section in the object file. */
708 #define TEXT_SECTION_ASM_OP "\t.text"
709 #define DATA_SECTION_ASM_OP "\t.data"
710 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
711
712
713 /* Define output to appear before the constant pool. */
714 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
715 do { \
716 if ((SIZE) > 0 || !TARGET_WINDOWED_ABI) \
717 { \
718 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
719 switch_to_section (function_section (FUNDECL)); \
720 fprintf (FILE, "\t.literal_position\n"); \
721 } \
722 } while (0)
723
724
725 /* A C statement (with or without semicolon) to output a constant in
726 the constant pool, if it needs special treatment. */
727 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
728 do { \
729 xtensa_output_literal (FILE, X, MODE, LABELNO); \
730 goto JUMPTO; \
731 } while (0)
732
733 /* How to start an assembler comment. */
734 #define ASM_COMMENT_START "#"
735
736 /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding
737 machinery, but the variable size register window save areas are too
738 complicated to efficiently describe with CFI entries. The CFA must
739 still be specified in DWARF so that DW_AT_frame_base is set correctly
740 for debugging. */
741 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0)
742 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0)
743 #define DWARF_ALT_FRAME_RETURN_COLUMN 16
744 #define DWARF_FRAME_REGISTERS (TARGET_WINDOWED_ABI \
745 ? DWARF_ALT_FRAME_RETURN_COLUMN \
746 : DWARF_ALT_FRAME_RETURN_COLUMN + 1)
747 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM)
748 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
749 (flag_pic \
750 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \
751 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
752 : DW_EH_PE_absptr)
753
754 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 10)
755
756 /* Emit a PC-relative relocation. */
757 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
758 do { \
759 fputs (integer_asm_op (SIZE, FALSE), FILE); \
760 assemble_name (FILE, LABEL); \
761 fputs ("@pcrel", FILE); \
762 } while (0)
763
764 /* Xtensa constant pool breaks the devices in crtstuff.c to control
765 section in where code resides. We have to write it as asm code. Use
766 a MOVI and let the assembler relax it -- for the .init and .fini
767 sections, the assembler knows to put the literal in the right
768 place. */
769 #if defined(__XTENSA_WINDOWED_ABI__)
770 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
771 asm (SECTION_OP "\n\
772 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
773 callx8\ta8\n" \
774 TEXT_SECTION_ASM_OP);
775 #elif defined(__XTENSA_CALL0_ABI__)
776 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
777 asm (SECTION_OP "\n\
778 movi\ta0, " USER_LABEL_PREFIX #FUNC "\n\
779 callx0\ta0\n" \
780 TEXT_SECTION_ASM_OP);
781 #endif