1  /* Definitions for option handling for SPARC.
       2     Copyright (C) 1996-2023 Free Software Foundation, Inc.
       3  
       4  This file is part of GCC.
       5  
       6  GCC is free software; you can redistribute it and/or modify
       7  it under the terms of the GNU General Public License as published by
       8  the Free Software Foundation; either version 3, or (at your option)
       9  any later version.
      10  
      11  GCC is distributed in the hope that it will be useful,
      12  but WITHOUT ANY WARRANTY; without even the implied warranty of
      13  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      14  GNU General Public License for more details.
      15  
      16  You should have received a copy of the GNU General Public License
      17  along with GCC; see the file COPYING3.  If not see
      18  <http://www.gnu.org/licenses/>.  */
      19  
      20  #ifndef SPARC_OPTS_H
      21  #define SPARC_OPTS_H
      22  
      23  /* SPARC processor type.
      24     These must match the values for the cpu attribute in sparc.md and
      25     the table in sparc_option_override.  */
      26  enum sparc_processor_type {
      27    PROCESSOR_V7,
      28    PROCESSOR_CYPRESS,
      29    PROCESSOR_V8,
      30    PROCESSOR_SUPERSPARC,
      31    PROCESSOR_HYPERSPARC,
      32    PROCESSOR_LEON,
      33    PROCESSOR_LEON3,
      34    PROCESSOR_LEON5,
      35    PROCESSOR_LEON3V7,
      36    PROCESSOR_SPARCLITE,
      37    PROCESSOR_F930,
      38    PROCESSOR_F934,
      39    PROCESSOR_SPARCLITE86X,
      40    PROCESSOR_SPARCLET,
      41    PROCESSOR_TSC701,
      42    PROCESSOR_V9,
      43    PROCESSOR_ULTRASPARC,
      44    PROCESSOR_ULTRASPARC3,
      45    PROCESSOR_NIAGARA,
      46    PROCESSOR_NIAGARA2,
      47    PROCESSOR_NIAGARA3,
      48    PROCESSOR_NIAGARA4,
      49    PROCESSOR_NIAGARA7,
      50    PROCESSOR_M8,
      51    PROCESSOR_NATIVE
      52  };
      53  
      54  /* SPARC-V9 code model type.  See sparc.h for the full description.  */
      55  enum sparc_code_model_type {
      56    CM_32,	/* 32-bit address space.  */
      57    CM_MEDLOW,	/* 32-bit address space.  */
      58    CM_MEDMID,	/* 44-bit address space.  */
      59    CM_MEDANY,	/* 64-bit address space.  */
      60    CM_EMBMEDANY	/* 64-bit address space.  */
      61  };
      62  
      63  /* SPARC memory model type.  See Appendix D in the SPARC-V9 manual
      64     for formal specification and Appendix J for more discussion.  */
      65  enum sparc_memory_model_type {
      66    SMM_DEFAULT,	/* Processor default.  */
      67    SMM_RMO,	/* Relaxed Memory Order.  */
      68    SMM_PSO,	/* Partial Store Order.  */
      69    SMM_TSO,	/* Total Store Order.  */
      70    SMM_SC	/* Sequential Consistency.  */
      71  };
      72  
      73  #endif