1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
24 #define RL78_MUL_G14 (rl78_mul_type == MUL_G14)
25
26 #define TARGET_G10 (rl78_cpu_type == CPU_G10)
27 #define TARGET_G13 (rl78_cpu_type == CPU_G13)
28 #define TARGET_G14 (rl78_cpu_type == CPU_G14)
29
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 builtin_define ("__RL78__"); \
34 builtin_assert ("cpu=RL78"); \
35 \
36 if (RL78_MUL_NONE) \
37 builtin_define ("__RL78_MUL_NONE__"); \
38 else if (RL78_MUL_G13) \
39 builtin_define ("__RL78_MUL_G13__"); \
40 else if (RL78_MUL_G14) \
41 builtin_define ("__RL78_MUL_G14__"); \
42 \
43 if (TARGET_G10) \
44 builtin_define ("__RL78_G10__"); \
45 else if (TARGET_G13) \
46 builtin_define ("__RL78_G13__"); \
47 else if (TARGET_G14) \
48 builtin_define ("__RL78_G14__"); \
49 } \
50 while (0)
51
52 #undef STARTFILE_SPEC
53 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
54
55 #undef ENDFILE_SPEC
56 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
57
58 #undef ASM_SPEC
59 #define ASM_SPEC "\
60 %{mrelax:-relax} \
61 %{mg10:--mg10} \
62 %{mg13:--mg13} \
63 %{mg14:--mg14} \
64 %{mrl78:--mg14} \
65 %{mcpu=g10:--mg10} \
66 %{mcpu=g13:--mg13} \
67 %{mcpu=g14:--mg14} \
68 %{mcpu=rl78:--mg14} \
69 "
70
71 #undef LINK_SPEC
72 #define LINK_SPEC "\
73 %{mrelax:-relax} \
74 %{!r:--gc-sections} \
75 "
76
77 #undef LIB_SPEC
78 #define LIB_SPEC " \
79 --start-group \
80 -lc \
81 -lsim \
82 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
83 --end-group \
84 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
85 "
86
87
88 #define BITS_BIG_ENDIAN 0
89 #define BYTES_BIG_ENDIAN 0
90 #define WORDS_BIG_ENDIAN 0
91
92 #ifdef IN_LIBGCC2
93 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
94 #define UNITS_PER_WORD 4
95 /* We have a problem with libgcc2. It only defines two versions of
96 each function, one for "int" and one for "long long". Ie it assumes
97 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
98 and we need a third set of functions. We explicitly define
99 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
100 to get the SI and DI versions from the libgcc2.c sources, and we
101 provide our own set of HI functions, which is why this
102 definition is surrounded by #ifndef..#endif. */
103 #ifndef LIBGCC2_UNITS_PER_WORD
104 #define LIBGCC2_UNITS_PER_WORD 4
105 #endif
106 #else
107 /* Actual width of a word, in units (bytes). */
108 #define UNITS_PER_WORD 1
109 #endif
110
111 #define SHORT_TYPE_SIZE 16
112 #define INT_TYPE_SIZE 16
113 #define LONG_TYPE_SIZE 32
114 #define LONG_LONG_TYPE_SIZE 64
115
116 #define FLOAT_TYPE_SIZE 32
117 #define DOUBLE_TYPE_SIZE 32 /*64*/
118 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
119
120 #define DEFAULT_SIGNED_CHAR 0
121
122 #define STRICT_ALIGNMENT 1
123 #define FUNCTION_BOUNDARY 8
124 #define BIGGEST_ALIGNMENT 16
125 #define STACK_BOUNDARY 16
126 #define PARM_BOUNDARY 16
127
128 #define STACK_GROWS_DOWNWARD 1
129 #define FRAME_GROWS_DOWNWARD 1
130 #define FIRST_PARM_OFFSET(FNDECL) 0
131
132 #define MAX_REGS_PER_ADDRESS 1
133
134 #define Pmode HImode
135 #define POINTER_SIZE 16
136 #undef SIZE_TYPE
137 #define SIZE_TYPE "unsigned int"
138 #undef PTRDIFF_TYPE
139 #define PTRDIFF_TYPE "int"
140 #undef WCHAR_TYPE
141 #define WCHAR_TYPE "long int"
142 #undef WCHAR_TYPE_SIZE
143 #define WCHAR_TYPE_SIZE BITS_PER_WORD
144 #define POINTERS_EXTEND_UNSIGNED 1
145 #define FUNCTION_MODE HImode
146 #define CASE_VECTOR_MODE Pmode
147 #define WORD_REGISTER_OPERATIONS 1
148 #define HAS_LONG_COND_BRANCH 0
149 #define HAS_LONG_UNCOND_BRANCH 0
150
151 #define MOVE_MAX 2
152
153 #define ADDR_SPACE_NEAR 1
154 #define ADDR_SPACE_FAR 2
155
156 #define HAVE_PRE_DECCREMENT 0
157 #define HAVE_POST_INCREMENT 0
158
159 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
160 #define SLOW_BYTE_ACCESS 0
161
162 #define STORE_FLAG_VALUE 1
163 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
164
165
166 /* The RL78 has four register banks. Normal operation uses RB0 as
167 real registers, RB1 and RB2 as "virtual" registers (because we know
168 they'll be there, and not used as variables), and RB3 is reserved
169 for interrupt handlers. The virtual registers are accessed as
170 SADDRs:
171
172 FFEE0-FFEE7 RB0
173 FFEE8-FFEEF RB1
174 FFEF0-FFEF7 RB2
175 FFEF8-FFEFF RB3
176 */
177 #define REGISTER_NAMES \
178 { \
179 "x", "a", "c", "b", "e", "d", "l", "h", \
180 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
181 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
182 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
183 "sp", "ap", "psw", "es", "cs" \
184 }
185
186 #define ADDITIONAL_REGISTER_NAMES \
187 { \
188 { "ax", 0 }, \
189 { "bc", 2 }, \
190 { "de", 4 }, \
191 { "hl", 6 }, \
192 { "rp0", 0 }, \
193 { "rp1", 2 }, \
194 { "rp2", 4 }, \
195 { "rp3", 6 }, \
196 { "r0", 0 }, \
197 { "r1", 1 }, \
198 { "r2", 2 }, \
199 { "r3", 3 }, \
200 { "r4", 4 }, \
201 { "r5", 5 }, \
202 { "r6", 6 }, \
203 { "r7", 7 }, \
204 }
205
206 enum reg_class
207 {
208 NO_REGS, /* No registers in set. */
209 XREG,
210 AREG,
211 AXREG,
212 CREG,
213 BREG,
214 BCREG,
215 EREG,
216 DREG,
217 DEREG,
218 LREG,
219 HREG,
220 HLREG,
221 IDX_REGS,
222 QI_REGS,
223 SPREG,
224 R8W_REGS,
225 R10W_REGS,
226 INT_REGS,
227 V_REGS, /* Virtual registers. */
228 GR_REGS, /* Integer registers. */
229 PSWREG,
230 ALL_REGS, /* All registers. */
231 LIM_REG_CLASSES /* Max value + 1. */
232 };
233
234 #define REG_CLASS_NAMES \
235 { \
236 "NO_REGS", \
237 "XREG", \
238 "AREG", \
239 "AXREG", \
240 "CREG", \
241 "BREG", \
242 "BCREG", \
243 "EREG", \
244 "DREG", \
245 "DEREG", \
246 "LREG", \
247 "HREG", \
248 "HLREG", \
249 "IDX_REGS", \
250 "QI_REGS", \
251 "SPREG", \
252 "R8W_REGS", \
253 "R10W_REGS", \
254 "INT_REGS", \
255 "V_REGS", \
256 "GR_REGS", \
257 "PSWREG", \
258 "ALL_REGS" \
259 }
260
261 /* Note that no class may include the second register in $fp, because
262 we treat $fp as a single HImode register. */
263 #define REG_CLASS_CONTENTS \
264 { \
265 { 0x00000000, 0x00000000 }, /* No registers, */ \
266 { 0x00000001, 0x00000000 }, \
267 { 0x00000002, 0x00000000 }, \
268 { 0x00000003, 0x00000000 }, \
269 { 0x00000004, 0x00000000 }, \
270 { 0x00000008, 0x00000000 }, \
271 { 0x0000000c, 0x00000000 }, \
272 { 0x00000010, 0x00000000 }, \
273 { 0x00000020, 0x00000000 }, \
274 { 0x00000030, 0x00000000 }, \
275 { 0x00000040, 0x00000000 }, \
276 { 0x00000080, 0x00000000 }, \
277 { 0x000000c0, 0x00000000 }, \
278 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
279 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
280 { 0x00000000, 0x00000001 }, /* SP */ \
281 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
282 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
283 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
284 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
285 { 0xff7fff00, 0x00000002 }, /* General registers. */ \
286 { 0x04000000, 0x00000004 }, /* PSW. */ \
287 { 0xff7fffff, 0x0000001f } /* All registers. */ \
288 }
289
290 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
291 #define N_REG_CLASSES (int) LIM_REG_CLASSES
292 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
293 + UNITS_PER_WORD - 1) \
294 / UNITS_PER_WORD)
295
296 #define GENERAL_REGS GR_REGS
297 #define BASE_REG_CLASS V_REGS
298 #define INDEX_REG_CLASS V_REGS
299
300 #define FIRST_PSEUDO_REGISTER 37
301
302 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
303 ? GR_REGS : NO_REGS)
304
305 #define FRAME_POINTER_REGNUM 22
306 #define STACK_POINTER_REGNUM 32
307 #define ARG_POINTER_REGNUM 33
308 #define CC_REGNUM 34
309 #define FUNC_RETURN_REGNUM 8
310 #define STATIC_CHAIN_REGNUM 14
311
312 /* Trampolines are implemented with a separate data stack. The memory
313 on stack only holds the function pointer for the chosen stub.
314 */
315
316 #define TRAMPOLINE_SIZE 4
317 #define TRAMPOLINE_ALIGNMENT 16
318
319 #define ELIMINABLE_REGS \
320 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
321 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
322 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
323
324 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
325 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
326
327
328 #define FUNCTION_ARG_REGNO_P(N) 0
329 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
330 #define DEFAULT_PCC_STRUCT_RETURN 0
331
332 #define FIXED_REGISTERS \
333 { \
334 1,1,1,1, 1,1,1,1, \
335 0,0,0,0, 0,0,0,0, \
336 0,0,0,0, 0,0,1,1, \
337 1,1,1,1, 1,1,1,1, \
338 0, 1, 0, 1, 1 \
339 }
340
341 #define CALL_USED_REGISTERS \
342 { \
343 1,1,1,1, 1,1,1,1, \
344 1,1,1,1, 1,1,1,1, \
345 0,0,0,0, 0,0,1,1, \
346 1,1,1,1, 1,1,1,1, \
347 0, 1, 1, 1, 1 \
348 }
349
350 #define LIBCALL_VALUE(MODE) \
351 gen_rtx_REG ((MODE), \
352 FUNC_RETURN_REGNUM)
353
354 /* Order of allocation of registers. */
355
356 #define REG_ALLOC_ORDER \
357 { 8, 9, 10, 11, 12, 13, 14, 15, \
358 16, 17, 18, 19, 20, 21, 22, 23, \
359 0, 1, 6, 7, 2, 3, 4, 5, \
360 24, 25, 26, 27, 28, 29, 30, 31, \
361 32, 33, 34 \
362 }
363
364 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
365 (IN_RANGE ((REGNO), (MIN), (MAX)) \
366 || (reg_renumber != NULL \
367 && reg_renumber[(REGNO)] >= (MIN) \
368 && reg_renumber[(REGNO)] <= (MAX)))
369
370 #ifdef REG_OK_STRICT
371 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
372 #else
373 #define REGNO_OK_FOR_BASE_P(regno) 1
374 #endif
375
376 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
377
378 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
379 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
380
381 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
382 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
383
384 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
385 ((COUNT) == 0 \
386 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
387 : NULL_RTX)
388
389 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
390
391 #define ACCUMULATE_OUTGOING_ARGS 1
392
393 typedef unsigned int CUMULATIVE_ARGS;
394
395 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
396 (CUM) = 0
397
398
399 /* FIXME */
400 #define NO_PROFILE_COUNTERS 1
401 #define PROFILE_BEFORE_PROLOGUE 1
402
403 #define FUNCTION_PROFILER(FILE, LABELNO) \
404 fprintf (FILE, "\tbsr\t__mcount\n");
405
406
407 #define TEXT_SECTION_ASM_OP ".text"
408 #define DATA_SECTION_ASM_OP ".data"
409 #define BSS_SECTION_ASM_OP ".bss"
410 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
411 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
412
413 #define ASM_COMMENT_START " ;"
414 #define ASM_APP_ON ""
415 #define ASM_APP_OFF ""
416 #define LOCAL_LABEL_PREFIX ".L"
417 #undef USER_LABEL_PREFIX
418 #define USER_LABEL_PREFIX "_"
419
420 #define GLOBAL_ASM_OP "\t.global\t"
421
422 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
423 fprintf (FILE, "\t.long .L%d\n", VALUE)
424
425 /* This is how to output an element of a case-vector that is relative.
426 Note: The local label referenced by the "3b" below is emitted by
427 the tablejump insn. */
428
429 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
430 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
431
432
433 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM))
434
435 #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM))
436
437 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
438 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
439
440 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
441 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
442
443 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
444 do \
445 { \
446 if ((LOG) == 0) \
447 break; \
448 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
449 } \
450 while (0)
451
452 /* For PIC put jump tables into the text section so that the offsets that
453 they contain are always computed between two same-section symbols. */
454 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
455
456 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
457 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
458
459 /* Like REG_P except that this macro is true for SET expressions. */
460 #define SET_P(rtl) (GET_CODE (rtl) == SET)
461
462 #undef PREFERRED_DEBUGGING_TYPE
463 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
464
465 #undef DWARF2_ADDR_SIZE
466 #define DWARF2_ADDR_SIZE 4
467
468 #define DWARF2_ASM_LINE_DEBUG_INFO 1
469
470 #define EXIT_IGNORE_STACK 0
471 #define INCOMING_FRAME_SP_OFFSET 4
472
473
474 #define BRANCH_COST(SPEED,PREDICT) 1
475 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
476
477 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
478 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
479
480 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
481
482 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
483 #define DWARF2_UNWIND_INFO 0
484
485 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()