1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_RISCV_PROTOS_H
23 #define GCC_RISCV_PROTOS_H
24
25 /* Symbol types we understand. The order of this list must match that of
26 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
27 enum riscv_symbol_type {
28 SYMBOL_ABSOLUTE,
29 SYMBOL_PCREL,
30 SYMBOL_GOT_DISP,
31 SYMBOL_TLS,
32 SYMBOL_TLS_LE,
33 SYMBOL_TLS_IE,
34 SYMBOL_TLS_GD
35 };
36 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
37
38 /* Routines implemented in riscv.cc. */
39 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
40 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
41 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
42 extern int riscv_address_insns (rtx, machine_mode, bool);
43 extern int riscv_const_insns (rtx);
44 extern int riscv_split_const_insns (rtx);
45 extern int riscv_load_store_insns (rtx, rtx_insn *);
46 extern rtx riscv_emit_move (rtx, rtx);
47 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool);
48 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
49 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
50 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool);
51 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
52 extern rtx riscv_subword (rtx, bool);
53 extern bool riscv_split_64bit_move_p (rtx, rtx);
54 extern void riscv_split_doubleword_move (rtx, rtx);
55 extern const char *riscv_output_move (rtx, rtx);
56 extern const char *riscv_output_return ();
57
58 #ifdef RTX_CODE
59 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
60 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
61 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
62 #endif
63 extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
64 extern rtx riscv_legitimize_call_address (rtx);
65 extern void riscv_set_return_address (rtx, rtx);
66 extern bool riscv_expand_block_move (rtx, rtx, rtx);
67 extern rtx riscv_return_addr (int, rtx);
68 extern poly_int64 riscv_initial_elimination_offset (int, int);
69 extern void riscv_expand_prologue (void);
70 extern void riscv_expand_epilogue (int);
71 extern bool riscv_epilogue_uses (unsigned int);
72 extern bool riscv_can_use_return_insn (void);
73 extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
74 extern bool riscv_expand_block_move (rtx, rtx, rtx);
75 extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
76 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
77 extern bool riscv_gpr_save_operation_p (rtx);
78 extern void riscv_reinit (void);
79 extern poly_uint64 riscv_regmode_natural_size (machine_mode);
80 extern bool riscv_v_ext_vector_mode_p (machine_mode);
81 extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
82 extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
83 extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
84
85 /* Routines implemented in riscv-c.cc. */
86 void riscv_cpu_cpp_builtins (cpp_reader *);
87 void riscv_register_pragmas (void);
88
89 /* Routines implemented in riscv-builtins.cc. */
90 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
91 extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
92 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
93 extern tree riscv_builtin_decl (unsigned int, bool);
94 extern void riscv_init_builtins (void);
95
96 /* Routines implemented in riscv-common.cc. */
97 extern std::string riscv_arch_str (bool version_p = true);
98 extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
99
100 extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
101
102 rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
103 rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
104
105 /* Information about one CPU we know about. */
106 struct riscv_cpu_info {
107 /* This CPU's canonical name. */
108 const char *name;
109
110 /* Default arch for this CPU, could be NULL if no default arch. */
111 const char *arch;
112
113 /* Which automaton to use for tuning. */
114 const char *tune;
115 };
116
117 extern const riscv_cpu_info *riscv_find_cpu (const char *);
118
119 /* Routines implemented in riscv-selftests.cc. */
120 #if CHECKING_P
121 namespace selftest {
122 void riscv_run_selftests (void);
123 } // namespace selftest
124 #endif
125
126 namespace riscv_vector {
127 #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
128 #define RVV_VUNDEF(MODE) \
129 gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \
130 UNSPEC_VUNDEF)
131 enum vlmul_type
132 {
133 LMUL_1 = 0,
134 LMUL_2 = 1,
135 LMUL_4 = 2,
136 LMUL_8 = 3,
137 LMUL_RESERVED = 4,
138 LMUL_F8 = 5,
139 LMUL_F4 = 6,
140 LMUL_F2 = 7,
141 NUM_LMUL = 8
142 };
143
144 enum avl_type
145 {
146 NONVLMAX,
147 VLMAX,
148 };
149 /* Routines implemented in riscv-vector-builtins.cc. */
150 void init_builtins (void);
151 const char *mangle_builtin_type (const_tree);
152 #ifdef GCC_TARGET_H
153 bool verify_type_context (location_t, type_context_kind, const_tree, bool);
154 #endif
155 void handle_pragma_vector (void);
156 tree builtin_decl (unsigned, bool);
157 gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
158 rtx expand_builtin (unsigned int, tree, rtx);
159 bool check_builtin_call (location_t, vec<location_t>, unsigned int,
160 tree, unsigned int, tree *);
161 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
162 bool legitimize_move (rtx, rtx, machine_mode);
163 void emit_vlmax_vsetvl (machine_mode, rtx);
164 void emit_hard_vlmax_vsetvl (machine_mode, rtx);
165 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
166 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
167 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
168 enum vlmul_type get_vlmul (machine_mode);
169 unsigned int get_ratio (machine_mode);
170 int get_ta (rtx);
171 int get_ma (rtx);
172 int get_avl_type (rtx);
173 unsigned int calculate_ratio (unsigned int, enum vlmul_type);
174 enum tail_policy
175 {
176 TAIL_UNDISTURBED = 0,
177 TAIL_AGNOSTIC = 1,
178 TAIL_ANY = 2,
179 };
180
181 enum mask_policy
182 {
183 MASK_UNDISTURBED = 0,
184 MASK_AGNOSTIC = 1,
185 MASK_ANY = 2,
186 };
187 enum tail_policy get_prefer_tail_policy ();
188 enum mask_policy get_prefer_mask_policy ();
189 rtx get_avl_type_rtx (enum avl_type);
190 opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
191 bool simm5_p (rtx);
192 bool neg_simm5_p (rtx);
193 #ifdef RTX_CODE
194 bool has_vi_variant_p (rtx_code, rtx);
195 #endif
196 bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, machine_mode,
197 bool, void (*)(rtx *, rtx));
198 rtx gen_scalar_move_mask (machine_mode);
199
200 /* RVV vector register sizes.
201 TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
202 support other values in the future. */
203 enum vlen_enum
204 {
205 RVV_32 = 32,
206 RVV_64 = 64,
207 RVV_65536 = 65536
208 };
209 bool slide1_sew64_helper (int, machine_mode, machine_mode,
210 machine_mode, rtx *);
211 rtx gen_avl_for_scalar_move (rtx);
212 }
213
214 /* We classify builtin types into two classes:
215 1. General builtin class which is defined in riscv_builtins.
216 2. Vector builtin class which is a special builtin architecture
217 that implement intrinsic short into "pragma". */
218 enum riscv_builtin_class
219 {
220 RISCV_BUILTIN_GENERAL,
221 RISCV_BUILTIN_VECTOR
222 };
223
224 const unsigned int RISCV_BUILTIN_SHIFT = 1;
225
226 /* Mask that selects the riscv_builtin_class part of a function code. */
227 const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
228
229 /* Routines implemented in thead.cc. */
230 extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
231 extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
232 extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
233 machine_mode,
234 int, HOST_WIDE_INT,
235 int, HOST_WIDE_INT);
236 extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
237 #ifdef RTX_CODE
238 extern const char*
239 th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
240 #endif
241
242 #endif /* ! GCC_RISCV_PROTOS_H */