1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2016-2023 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef GCC_RISCV_OPTS_H
22 #define GCC_RISCV_OPTS_H
23
24 enum riscv_abi_type {
25 ABI_ILP32,
26 ABI_ILP32E,
27 ABI_ILP32F,
28 ABI_ILP32D,
29 ABI_LP64,
30 ABI_LP64F,
31 ABI_LP64D
32 };
33 extern enum riscv_abi_type riscv_abi;
34
35 enum riscv_code_model {
36 CM_MEDLOW,
37 CM_MEDANY,
38 CM_PIC
39 };
40 extern enum riscv_code_model riscv_cmodel;
41
42 enum riscv_isa_spec_class {
43 ISA_SPEC_CLASS_NONE,
44
45 ISA_SPEC_CLASS_2P2,
46 ISA_SPEC_CLASS_20190608,
47 ISA_SPEC_CLASS_20191213
48 };
49
50 extern enum riscv_isa_spec_class riscv_isa_spec;
51
52 /* Keep this list in sync with define_attr "tune" in riscv.md. */
53 enum riscv_microarchitecture_type {
54 generic,
55 sifive_7
56 };
57 extern enum riscv_microarchitecture_type riscv_microarchitecture;
58
59 enum riscv_align_data {
60 riscv_align_data_type_xlen,
61 riscv_align_data_type_natural
62 };
63
64 /* Where to get the canary for the stack protector. */
65 enum stack_protector_guard {
66 SSP_TLS, /* per-thread canary in TLS block */
67 SSP_GLOBAL /* global canary */
68 };
69
70 enum riscv_multilib_select_kind {
71 /* Select multilib by builtin way. */
72 select_by_builtin,
73 /* Select multilib by ABI, arch and code model. */
74 select_by_abi_arch_cmodel,
75 /* Select multilib by ABI only. */
76 select_by_abi,
77 };
78
79 #define MASK_ZICSR (1 << 0)
80 #define MASK_ZIFENCEI (1 << 1)
81
82 #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
83 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
84
85 #define MASK_ZAWRS (1 << 0)
86 #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
87
88 #define MASK_ZBA (1 << 0)
89 #define MASK_ZBB (1 << 1)
90 #define MASK_ZBC (1 << 2)
91 #define MASK_ZBS (1 << 3)
92
93 #define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
94 #define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
95 #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
96 #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
97
98 #define MASK_ZFINX (1 << 0)
99 #define MASK_ZDINX (1 << 1)
100 #define MASK_ZHINX (1 << 2)
101 #define MASK_ZHINXMIN (1 << 3)
102
103 #define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
104 #define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
105 #define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
106 #define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
107
108 #define MASK_ZBKB (1 << 0)
109 #define MASK_ZBKC (1 << 1)
110 #define MASK_ZBKX (1 << 2)
111 #define MASK_ZKNE (1 << 3)
112 #define MASK_ZKND (1 << 4)
113 #define MASK_ZKNH (1 << 5)
114 #define MASK_ZKR (1 << 6)
115 #define MASK_ZKSED (1 << 7)
116 #define MASK_ZKSH (1 << 8)
117 #define MASK_ZKT (1 << 9)
118
119 #define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
120 #define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
121 #define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
122 #define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
123 #define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
124 #define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
125 #define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
126 #define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
127 #define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
128 #define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
129
130 #define MASK_VECTOR_ELEN_32 (1 << 0)
131 #define MASK_VECTOR_ELEN_64 (1 << 1)
132 #define MASK_VECTOR_ELEN_FP_32 (1 << 2)
133 #define MASK_VECTOR_ELEN_FP_64 (1 << 3)
134
135 #define TARGET_VECTOR_ELEN_32 \
136 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
137 #define TARGET_VECTOR_ELEN_64 \
138 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
139 #define TARGET_VECTOR_ELEN_FP_32 \
140 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
141 #define TARGET_VECTOR_ELEN_FP_64 \
142 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
143
144 #define MASK_ZVL32B (1 << 0)
145 #define MASK_ZVL64B (1 << 1)
146 #define MASK_ZVL128B (1 << 2)
147 #define MASK_ZVL256B (1 << 3)
148 #define MASK_ZVL512B (1 << 4)
149 #define MASK_ZVL1024B (1 << 5)
150 #define MASK_ZVL2048B (1 << 6)
151 #define MASK_ZVL4096B (1 << 7)
152 #define MASK_ZVL8192B (1 << 8)
153 #define MASK_ZVL16384B (1 << 9)
154 #define MASK_ZVL32768B (1 << 10)
155 #define MASK_ZVL65536B (1 << 11)
156
157 #define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
158 #define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
159 #define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
160 #define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
161 #define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
162 #define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
163 #define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
164 #define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
165 #define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
166 #define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
167 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
168 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
169
170 #define MASK_ZICBOZ (1 << 0)
171 #define MASK_ZICBOM (1 << 1)
172 #define MASK_ZICBOP (1 << 2)
173
174 #define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
175 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
176 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
177
178 #define MASK_ZFHMIN (1 << 0)
179 #define MASK_ZFH (1 << 1)
180
181 #define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
182 #define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
183
184 #define MASK_ZMMUL (1 << 0)
185 #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
186
187 #define MASK_SVINVAL (1 << 0)
188 #define MASK_SVNAPOT (1 << 1)
189
190 #define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
191 #define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
192
193 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
194 set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
195 popcount to caclulate the minimal VLEN. */
196 #define TARGET_MIN_VLEN \
197 ((riscv_zvl_flags == 0) \
198 ? 0 \
199 : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
200
201 #define MASK_XTHEADBA (1 << 0)
202 #define MASK_XTHEADBB (1 << 1)
203 #define MASK_XTHEADBS (1 << 2)
204 #define MASK_XTHEADCMO (1 << 3)
205 #define MASK_XTHEADCONDMOV (1 << 4)
206 #define MASK_XTHEADFMEMIDX (1 << 5)
207 #define MASK_XTHEADFMV (1 << 6)
208 #define MASK_XTHEADINT (1 << 7)
209 #define MASK_XTHEADMAC (1 << 8)
210 #define MASK_XTHEADMEMIDX (1 << 9)
211 #define MASK_XTHEADMEMPAIR (1 << 10)
212 #define MASK_XTHEADSYNC (1 << 11)
213
214 #define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
215 #define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
216 #define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
217 #define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
218 #define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
219 #define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
220 #define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
221 #define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
222 #define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
223 #define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
224 #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
225 #define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
226
227 #endif /* ! GCC_RISCV_OPTS_H */