1  /* Definitions for option handling of Andes NDS32 cpu for GNU compiler
       2     Copyright (C) 2012-2023 Free Software Foundation, Inc.
       3     Contributed by Andes Technology Corporation.
       4  
       5     This file is part of GCC.
       6  
       7     GCC is free software; you can redistribute it and/or modify it
       8     under the terms of the GNU General Public License as published
       9     by the Free Software Foundation; either version 3, or (at your
      10     option) any later version.
      11  
      12     GCC is distributed in the hope that it will be useful, but WITHOUT
      13     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
      14     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
      15     License for more details.
      16  
      17     You should have received a copy of the GNU General Public License
      18     along with GCC; see the file COPYING3.  If not see
      19     <http://www.gnu.org/licenses/>.  */
      20  
      21  #ifndef NDS32_OPTS_H
      22  #define NDS32_OPTS_H
      23  
      24  #define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
      25  #define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
      26  
      27  /* The various ANDES ISA.  */
      28  enum nds32_arch_type
      29  {
      30    ARCH_V2,
      31    ARCH_V3,
      32    ARCH_V3J,
      33    ARCH_V3M,
      34    ARCH_V3F,
      35    ARCH_V3S
      36  };
      37  
      38  /* The various ANDES CPU.  */
      39  enum nds32_cpu_type
      40  {
      41    CPU_N6,
      42    CPU_N7,
      43    CPU_N8,
      44    CPU_E8,
      45    CPU_N9,
      46    CPU_N10,
      47    CPU_GRAYWOLF,
      48    CPU_N12,
      49    CPU_N13,
      50    CPU_SIMPLE
      51  };
      52  
      53  /* The code model defines the address generation strategy.  */
      54  enum nds32_cmodel_type
      55  {
      56    CMODEL_SMALL,
      57    CMODEL_MEDIUM,
      58    CMODEL_LARGE
      59  };
      60  
      61  /* The code model defines the address generation strategy.  */
      62  enum nds32_ict_model_type
      63  {
      64    ICT_MODEL_SMALL,
      65    ICT_MODEL_LARGE
      66  };
      67  
      68  /* Multiply instruction configuration.  */
      69  enum nds32_mul_type
      70  {
      71    MUL_TYPE_FAST_1,
      72    MUL_TYPE_FAST_2,
      73    MUL_TYPE_SLOW
      74  };
      75  
      76  /* Register ports configuration.  */
      77  enum nds32_register_ports
      78  {
      79    REG_PORT_3R2W,
      80    REG_PORT_2R1W
      81  };
      82  
      83  /* Which ABI to use.  */
      84  enum abi_type
      85  {
      86    NDS32_ABI_V2,
      87    NDS32_ABI_V2_FP_PLUS
      88  };
      89  
      90  /* The various FPU number of registers.  */
      91  enum float_reg_number
      92  {
      93    NDS32_CONFIG_FPU_0,
      94    NDS32_CONFIG_FPU_1,
      95    NDS32_CONFIG_FPU_2,
      96    NDS32_CONFIG_FPU_3,
      97    NDS32_CONFIG_FPU_4,
      98    NDS32_CONFIG_FPU_5,
      99    NDS32_CONFIG_FPU_6,
     100    NDS32_CONFIG_FPU_7
     101  };
     102  
     103  #endif