1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.cc. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 enum mips_isa {
46 MIPS_ISA_MIPS1 = 1,
47 MIPS_ISA_MIPS2 = 2,
48 MIPS_ISA_MIPS3 = 3,
49 MIPS_ISA_MIPS4 = 4,
50 MIPS_ISA_MIPS32 = 32,
51 MIPS_ISA_MIPS32R2 = 33,
52 MIPS_ISA_MIPS32R3 = 34,
53 MIPS_ISA_MIPS32R5 = 36,
54 MIPS_ISA_MIPS32R6 = 37,
55 MIPS_ISA_MIPS64 = 64,
56 MIPS_ISA_MIPS64R2 = 65,
57 MIPS_ISA_MIPS64R3 = 66,
58 MIPS_ISA_MIPS64R5 = 68,
59 MIPS_ISA_MIPS64R6 = 69
60 };
61
62 /* Masks that affect tuning.
63
64 PTF_AVOID_BRANCHLIKELY_SPEED
65 Set if it is usually not profitable to use branch-likely instructions
66 for this target when optimizing code for speed, typically because
67 the branches are always predicted taken and so incur a large overhead
68 when not taken.
69
70 PTF_AVOID_BRANCHLIKELY_SIZE
71 As above but when optimizing for size.
72
73 PTF_AVOID_BRANCHLIKELY_ALWAYS
74 As above but regardless of whether we optimize for speed or size.
75
76 PTF_AVOID_IMADD
77 Set if it is usually not profitable to use the integer MADD or MSUB
78 instructions because of the overhead of getting the result out of
79 the HI/LO registers. */
80
81 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
82 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
83 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
84 PTF_AVOID_BRANCHLIKELY_SIZE)
85 #define PTF_AVOID_IMADD 0x4
86
87 /* Information about one recognized processor. Defined here for the
88 benefit of TARGET_CPU_CPP_BUILTINS. */
89 struct mips_cpu_info {
90 /* The 'canonical' name of the processor as far as GCC is concerned.
91 It's typically a manufacturer's prefix followed by a numerical
92 designation. It should be lowercase. */
93 const char *name;
94
95 /* The internal processor number that most closely matches this
96 entry. Several processors can have the same value, if there's no
97 difference between them from GCC's point of view. */
98 enum processor cpu;
99
100 /* The ISA level that the processor implements. */
101 enum mips_isa isa;
102
103 /* A mask of PTF_* values. */
104 unsigned int tune_flags;
105 };
106
107 #include "config/mips/mips-opts.h"
108
109 /* Macros to silence warnings about numbers being signed in traditional
110 C and unsigned in ISO C when compiled on 32-bit hosts. */
111
112 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
113 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
114 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
115
116
117 /* Run-time compilation parameters selecting different hardware subsets. */
118
119 /* True if we are generating position-independent VxWorks RTP code. */
120 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
121
122 /* Compact branches must not be used if the user either selects the
123 'never' policy or the 'optimal' / 'always' policy on a core that lacks
124 compact branch instructions. */
125 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
126
127 /* Compact branches may be used if the user either selects the
128 'always' policy or the 'optimal' policy on a core that supports
129 compact branch instructions. */
130 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
131 || (mips_cb == MIPS_CB_OPTIMAL \
132 && ISA_HAS_COMPACT_BRANCHES))
133
134 /* Compact branches must always be generated if the user selects
135 the 'always' policy on a core support compact branches,
136 or the 'optimal' policy on a core that lacks delay slot branch instructions. */
137 #define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS \
138 && ISA_HAS_COMPACT_BRANCHES) \
139 || (mips_cb == MIPS_CB_OPTIMAL \
140 && !ISA_HAS_DELAY_SLOTS))
141
142 /* Special handling for JRC that exists in microMIPSR3 as well as R6
143 ISAs with full compact branch support. */
144 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
145 || TARGET_MICROMIPS) \
146 && mips_cb != MIPS_CB_NEVER)
147
148 /* True if the output file is marked as ".abicalls; .option pic0"
149 (-call_nonpic). */
150 #define TARGET_ABICALLS_PIC0 \
151 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
152
153 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
154 #define TARGET_ABICALLS_PIC2 \
155 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
156
157 /* True if the call patterns should be split into a jalr followed by
158 an instruction to restore $gp. It is only safe to split the load
159 from the call when every use of $gp is explicit.
160
161 See mips_must_initialize_gp_p for details about how we manage the
162 global pointer. */
163
164 #define TARGET_SPLIT_CALLS \
165 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
166
167 /* True if we're generating a form of -mabicalls in which we can use
168 operators like %hi and %lo to refer to locally-binding symbols.
169 We can only do this for -mno-shared, and only then if we can use
170 relocation operations instead of assembly macros. It isn't really
171 worth using absolute sequences for 64-bit symbols because GOT
172 accesses are so much shorter. */
173
174 #define TARGET_ABSOLUTE_ABICALLS \
175 (TARGET_ABICALLS \
176 && !TARGET_SHARED \
177 && TARGET_EXPLICIT_RELOCS \
178 && !ABI_HAS_64BIT_SYMBOLS)
179
180 /* True if we can optimize sibling calls. For simplicity, we only
181 handle cases in which call_insn_operand will reject invalid
182 sibcall addresses. There are two cases in which this isn't true:
183
184 - TARGET_MIPS16. call_insn_operand accepts constant addresses
185 but there is no direct jump instruction. It isn't worth
186 using sibling calls in this case anyway; they would usually
187 be longer than normal calls.
188
189 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
190 accepts global constants, but all sibcalls must be indirect. */
191 #define TARGET_SIBCALLS \
192 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
193
194 /* True if we need to use a global offset table to access some symbols. */
195 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
196
197 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
198 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
199
200 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
201 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
202
203 /* True if we should use .cprestore to store to the cprestore slot.
204
205 We continue to use .cprestore for explicit-reloc code so that JALs
206 inside inline asms will work correctly. */
207 #define TARGET_CPRESTORE_DIRECTIVE \
208 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
209
210 /* True if we can use the J and JAL instructions. */
211 #define TARGET_ABSOLUTE_JUMPS \
212 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
213
214 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
215 This is true for both the PIC and non-PIC VxWorks RTP modes. */
216 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
217
218 /* True if .gpword or .gpdword should be used for switch tables. */
219 #define TARGET_GPWORD \
220 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
221
222 /* True if the output must have a writable .eh_frame.
223 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
224 #ifdef HAVE_LD_PERSONALITY_RELAXATION
225 #define TARGET_WRITABLE_EH_FRAME 0
226 #else
227 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
228 #endif
229
230 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
231 #ifdef HAVE_AS_DSPR1_MULT
232 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
233 #else
234 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
235 #endif
236
237 /* ISA has LSA available. */
238 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
239
240 /* ISA has DLSA available. */
241 #define ISA_HAS_DLSA (TARGET_64BIT \
242 && (mips_isa_rev >= 6 \
243 || ISA_HAS_MSA))
244
245 /* ISA load/store instructions can handle unaligned address */
246 #define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \
247 && (mips_isa_rev >= 6))
248
249 /* The ISA compression flags that are currently in effect. */
250 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
251
252 /* Generate mips16 code */
253 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
254 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
255 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32)
256 /* Generate mips16e register save/restore sequences. */
257 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
258
259 /* True if we're generating a form of MIPS16 code in which general
260 text loads are allowed. */
261 #define TARGET_MIPS16_TEXT_LOADS \
262 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
263
264 /* True if we're generating a form of MIPS16 code in which PC-relative
265 loads are allowed. */
266 #define TARGET_MIPS16_PCREL_LOADS \
267 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
268
269 /* Generic ISA defines. */
270 #define ISA_MIPS1 (mips_isa == MIPS_ISA_MIPS1)
271 #define ISA_MIPS2 (mips_isa == MIPS_ISA_MIPS2)
272 #define ISA_MIPS3 (mips_isa == MIPS_ISA_MIPS3)
273 #define ISA_MIPS4 (mips_isa == MIPS_ISA_MIPS4)
274 #define ISA_MIPS32 (mips_isa == MIPS_ISA_MIPS32)
275 #define ISA_MIPS32R2 (mips_isa == MIPS_ISA_MIPS32R2)
276 #define ISA_MIPS32R3 (mips_isa == MIPS_ISA_MIPS32R3)
277 #define ISA_MIPS32R5 (mips_isa == MIPS_ISA_MIPS32R5)
278 #define ISA_MIPS32R6 (mips_isa == MIPS_ISA_MIPS32R6)
279 #define ISA_MIPS64 (mips_isa == MIPS_ISA_MIPS64)
280 #define ISA_MIPS64R2 (mips_isa == MIPS_ISA_MIPS64R2)
281 #define ISA_MIPS64R3 (mips_isa == MIPS_ISA_MIPS64R3)
282 #define ISA_MIPS64R5 (mips_isa == MIPS_ISA_MIPS64R5)
283 #define ISA_MIPS64R6 (mips_isa == MIPS_ISA_MIPS64R6)
284
285 /* Architecture target defines. */
286 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
287 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
288 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
289 #define TARGET_GS464 (mips_arch == PROCESSOR_GS464)
290 #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E)
291 #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E)
292 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
293 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
294 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
295 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
296 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
297 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
298 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
299 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
300 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
301 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
302 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
303 || mips_arch == PROCESSOR_OCTEON2 \
304 || mips_arch == PROCESSOR_OCTEON3)
305 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
306 || mips_arch == PROCESSOR_OCTEON3)
307 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
308 || mips_arch == PROCESSOR_SB1A)
309 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
310 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
311
312 /* Scheduling target defines. */
313 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
314 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
315 || mips_tune == PROCESSOR_24KF2_1 \
316 || mips_tune == PROCESSOR_24KF1_1)
317 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
318 || mips_tune == PROCESSOR_74KF2_1 \
319 || mips_tune == PROCESSOR_74KF1_1 \
320 || mips_tune == PROCESSOR_74KF3_2)
321 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
322 || mips_tune == PROCESSOR_LOONGSON_2F)
323 #define TUNE_GS464 (mips_tune == PROCESSOR_GS464)
324 #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E)
325 #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E)
326 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
327 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
328 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
329 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
330 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
331 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
332 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
333 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
334 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
335 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
336 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
337 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
338 || mips_tune == PROCESSOR_OCTEON2 \
339 || mips_tune == PROCESSOR_OCTEON3)
340 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
341 || mips_tune == PROCESSOR_SB1A)
342 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
343 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
344 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
345
346 /* True if the pre-reload scheduler should try to create chains of
347 multiply-add or multiply-subtract instructions. For example,
348 suppose we have:
349
350 t1 = a * b
351 t2 = t1 + c * d
352 t3 = e * f
353 t4 = t3 - g * h
354
355 t1 will have a higher priority than t2 and t3 will have a higher
356 priority than t4. However, before reload, there is no dependence
357 between t1 and t3, and they can often have similar priorities.
358 The scheduler will then tend to prefer:
359
360 t1 = a * b
361 t3 = e * f
362 t2 = t1 + c * d
363 t4 = t3 - g * h
364
365 which stops us from making full use of macc/madd-style instructions.
366 This sort of situation occurs frequently in Fourier transforms and
367 in unrolled loops.
368
369 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
370 queue so that chained multiply-add and multiply-subtract instructions
371 appear ahead of any other instruction that is likely to clobber lo.
372 In the example above, if t2 and t3 become ready at the same time,
373 the code ensures that t2 is scheduled first.
374
375 Multiply-accumulate instructions are a bigger win for some targets
376 than others, so this macro is defined on an opt-in basis. */
377 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
378 || TUNE_MIPS4120 \
379 || TUNE_MIPS4130 \
380 || TUNE_24K \
381 || TUNE_P5600)
382
383 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
384 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
385
386 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
387 directly accessible, while the command-line options select
388 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
389 in use. */
390 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
391 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
392
393 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
394 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
395 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
396
397 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
398 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
399 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
400 && !TARGET_ODD_SPREG)
401
402 /* False if SC acts as a memory barrier with respect to itself,
403 otherwise a SYNC will be emitted after SC for atomic operations
404 that require ordering between the SC and following loads and
405 stores. It does not tell anything about ordering of loads and
406 stores prior to and following the SC, only about the SC itself and
407 those loads and stores follow it. */
408 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
409
410 /* Define preprocessor macros for the -march and -mtune options.
411 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
412 processor. If INFO's canonical name is "foo", define PREFIX to
413 be "foo", and define an additional macro PREFIX_FOO. */
414 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
415 do \
416 { \
417 char *macro, *p; \
418 \
419 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
420 for (p = macro; *p != 0; p++) \
421 if (*p == '+') \
422 *p = 'P'; \
423 else \
424 *p = TOUPPER (*p); \
425 \
426 builtin_define (macro); \
427 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
428 free (macro); \
429 } \
430 while (0)
431
432 /* Target CPU builtins. */
433 #define TARGET_CPU_CPP_BUILTINS() \
434 do \
435 { \
436 builtin_assert ("machine=mips"); \
437 builtin_assert ("cpu=mips"); \
438 builtin_define ("__mips__"); \
439 builtin_define ("_mips"); \
440 \
441 /* We do this here because __mips is defined below and so we \
442 can't use builtin_define_std. We don't ever want to define \
443 "mips" for VxWorks because some of the VxWorks headers \
444 construct include filenames from a root directory macro, \
445 an architecture macro and a filename, where the architecture \
446 macro expands to 'mips'. If we define 'mips' to 1, the \
447 architecture macro expands to 1 as well. */ \
448 if (!flag_iso && !TARGET_VXWORKS) \
449 builtin_define ("mips"); \
450 \
451 if (TARGET_64BIT) \
452 builtin_define ("__mips64"); \
453 \
454 /* Treat _R3000 and _R4000 like register-size \
455 defines, which is how they've historically \
456 been used. */ \
457 if (TARGET_64BIT) \
458 { \
459 builtin_define_std ("R4000"); \
460 builtin_define ("_R4000"); \
461 } \
462 else \
463 { \
464 builtin_define_std ("R3000"); \
465 builtin_define ("_R3000"); \
466 } \
467 \
468 if (TARGET_FLOAT64) \
469 builtin_define ("__mips_fpr=64"); \
470 else if (TARGET_FLOATXX) \
471 builtin_define ("__mips_fpr=0"); \
472 else \
473 builtin_define ("__mips_fpr=32"); \
474 \
475 if (mips_base_compression_flags & MASK_MIPS16) \
476 builtin_define ("__mips16"); \
477 \
478 if (TARGET_MIPS3D) \
479 builtin_define ("__mips3d"); \
480 \
481 if (TARGET_SMARTMIPS) \
482 builtin_define ("__mips_smartmips"); \
483 \
484 if (mips_base_compression_flags & MASK_MICROMIPS) \
485 builtin_define ("__mips_micromips"); \
486 \
487 if (TARGET_MCU) \
488 builtin_define ("__mips_mcu"); \
489 \
490 if (TARGET_EVA) \
491 builtin_define ("__mips_eva"); \
492 \
493 if (TARGET_DSP) \
494 { \
495 builtin_define ("__mips_dsp"); \
496 if (TARGET_DSPR2) \
497 { \
498 builtin_define ("__mips_dspr2"); \
499 builtin_define ("__mips_dsp_rev=2"); \
500 } \
501 else \
502 builtin_define ("__mips_dsp_rev=1"); \
503 } \
504 \
505 if (ISA_HAS_MSA) \
506 { \
507 builtin_define ("__mips_msa"); \
508 builtin_define ("__mips_msa_width=128"); \
509 } \
510 \
511 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
512 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
513 \
514 if (ISA_MIPS1) \
515 { \
516 builtin_define ("__mips=1"); \
517 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
518 } \
519 else if (ISA_MIPS2) \
520 { \
521 builtin_define ("__mips=2"); \
522 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
523 } \
524 else if (ISA_MIPS3) \
525 { \
526 builtin_define ("__mips=3"); \
527 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
528 } \
529 else if (ISA_MIPS4) \
530 { \
531 builtin_define ("__mips=4"); \
532 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
533 } \
534 else if (mips_isa >= MIPS_ISA_MIPS32 \
535 && mips_isa < MIPS_ISA_MIPS64) \
536 { \
537 builtin_define ("__mips=32"); \
538 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
539 } \
540 else if (mips_isa >= MIPS_ISA_MIPS64) \
541 { \
542 builtin_define ("__mips=64"); \
543 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
544 } \
545 if (mips_isa_rev > 0) \
546 builtin_define_with_int_value ("__mips_isa_rev", \
547 mips_isa_rev); \
548 \
549 switch (mips_abi) \
550 { \
551 case ABI_32: \
552 builtin_define ("_ABIO32=1"); \
553 builtin_define ("_MIPS_SIM=_ABIO32"); \
554 break; \
555 \
556 case ABI_N32: \
557 builtin_define ("_ABIN32=2"); \
558 builtin_define ("_MIPS_SIM=_ABIN32"); \
559 break; \
560 \
561 case ABI_64: \
562 builtin_define ("_ABI64=3"); \
563 builtin_define ("_MIPS_SIM=_ABI64"); \
564 break; \
565 \
566 case ABI_O64: \
567 builtin_define ("_ABIO64=4"); \
568 builtin_define ("_MIPS_SIM=_ABIO64"); \
569 break; \
570 } \
571 \
572 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
573 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
574 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
575 builtin_define_with_int_value ("_MIPS_FPSET", \
576 32 / MAX_FPRS_PER_FMT); \
577 builtin_define_with_int_value ("_MIPS_SPFPSET", \
578 TARGET_ODD_SPREG ? 32 : 16); \
579 \
580 /* These defines reflect the ABI in use, not whether the \
581 FPU is directly accessible. */ \
582 if (TARGET_NO_FLOAT) \
583 builtin_define ("__mips_no_float"); \
584 else if (TARGET_HARD_FLOAT_ABI) \
585 builtin_define ("__mips_hard_float"); \
586 else \
587 builtin_define ("__mips_soft_float"); \
588 \
589 if (TARGET_SINGLE_FLOAT) \
590 builtin_define ("__mips_single_float"); \
591 \
592 if (TARGET_PAIRED_SINGLE_FLOAT) \
593 builtin_define ("__mips_paired_single_float"); \
594 \
595 if (mips_abs == MIPS_IEEE_754_2008) \
596 builtin_define ("__mips_abs2008"); \
597 \
598 if (mips_nan == MIPS_IEEE_754_2008) \
599 builtin_define ("__mips_nan2008"); \
600 \
601 if (TARGET_BIG_ENDIAN) \
602 { \
603 builtin_define_std ("MIPSEB"); \
604 builtin_define ("_MIPSEB"); \
605 } \
606 else \
607 { \
608 builtin_define_std ("MIPSEL"); \
609 builtin_define ("_MIPSEL"); \
610 } \
611 \
612 /* Whether calls should go through $25. The separate __PIC__ \
613 macro indicates whether abicalls code might use a GOT. */ \
614 if (TARGET_ABICALLS) \
615 builtin_define ("__mips_abicalls"); \
616 \
617 /* Whether Loongson vector modes are enabled. */ \
618 if (TARGET_LOONGSON_MMI) \
619 { \
620 builtin_define ("__mips_loongson_vector_rev"); \
621 builtin_define ("__mips_loongson_mmi"); \
622 } \
623 \
624 /* Whether Loongson EXT modes are enabled. */ \
625 if (TARGET_LOONGSON_EXT) \
626 { \
627 builtin_define ("__mips_loongson_ext"); \
628 if (TARGET_LOONGSON_EXT2) \
629 { \
630 builtin_define ("__mips_loongson_ext2"); \
631 builtin_define ("__mips_loongson_ext_rev=2"); \
632 } \
633 else \
634 builtin_define ("__mips_loongson_ext_rev=1"); \
635 } \
636 \
637 /* Historical Octeon macro. */ \
638 if (TARGET_OCTEON) \
639 builtin_define ("__OCTEON__"); \
640 \
641 if (TARGET_SYNCI) \
642 builtin_define ("__mips_synci"); \
643 \
644 /* Macros dependent on the C dialect. */ \
645 if (preprocessing_asm_p ()) \
646 { \
647 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
648 builtin_define ("_LANGUAGE_ASSEMBLY"); \
649 } \
650 else if (c_dialect_cxx ()) \
651 { \
652 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
653 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
654 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
655 } \
656 else \
657 { \
658 builtin_define_std ("LANGUAGE_C"); \
659 builtin_define ("_LANGUAGE_C"); \
660 } \
661 if (c_dialect_objc ()) \
662 { \
663 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
664 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
665 /* Bizarre, but retained for backwards compatibility. */ \
666 builtin_define_std ("LANGUAGE_C"); \
667 builtin_define ("_LANGUAGE_C"); \
668 } \
669 \
670 if (mips_abi == ABI_EABI) \
671 builtin_define ("__mips_eabi"); \
672 \
673 if (TARGET_CACHE_BUILTIN) \
674 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
675 if (!ISA_HAS_LXC1_SXC1) \
676 builtin_define ("__mips_no_lxc1_sxc1"); \
677 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
678 builtin_define ("__mips_no_madd4"); \
679 \
680 if (TARGET_CB_NEVER) \
681 builtin_define ("__mips_compact_branches_never"); \
682 else if (TARGET_CB_ALWAYS) \
683 builtin_define ("__mips_compact_branches_always"); \
684 else \
685 builtin_define ("__mips_compact_branches_optimal"); \
686 } \
687 while (0)
688
689 /* Default target_flags if no switches are specified */
690
691 #ifndef TARGET_DEFAULT
692 #define TARGET_DEFAULT 0
693 #endif
694
695 #ifndef TARGET_CPU_DEFAULT
696 #define TARGET_CPU_DEFAULT 0
697 #endif
698
699 #ifndef TARGET_ENDIAN_DEFAULT
700 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
701 #endif
702
703 #ifdef IN_LIBGCC2
704 #undef TARGET_64BIT
705 /* Make this compile time constant for libgcc2 */
706 #ifdef __mips64
707 #define TARGET_64BIT 1
708 #else
709 #define TARGET_64BIT 0
710 #endif
711 #endif /* IN_LIBGCC2 */
712
713 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
714 when compiled with hardware floating point. This is because MIPS16
715 code cannot save and restore the floating-point registers, which is
716 important if in a mixed MIPS16/non-MIPS16 environment. */
717
718 #ifdef IN_LIBGCC2
719 #if __mips_hard_float
720 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
721 #endif
722 #endif /* IN_LIBGCC2 */
723
724 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
725
726 #ifndef MULTILIB_ENDIAN_DEFAULT
727 #if TARGET_ENDIAN_DEFAULT == 0
728 #define MULTILIB_ENDIAN_DEFAULT "EL"
729 #else
730 #define MULTILIB_ENDIAN_DEFAULT "EB"
731 #endif
732 #endif
733
734 #ifndef MULTILIB_ISA_DEFAULT
735 #if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1
736 #define MULTILIB_ISA_DEFAULT "mips1"
737 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2
738 #define MULTILIB_ISA_DEFAULT "mips2"
739 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3
740 #define MULTILIB_ISA_DEFAULT "mips3"
741 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4
742 #define MULTILIB_ISA_DEFAULT "mips4"
743 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32
744 #define MULTILIB_ISA_DEFAULT "mips32"
745 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2
746 #define MULTILIB_ISA_DEFAULT "mips32r2"
747 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6
748 #define MULTILIB_ISA_DEFAULT "mips32r6"
749 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64
750 #define MULTILIB_ISA_DEFAULT "mips64"
751 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2
752 #define MULTILIB_ISA_DEFAULT "mips64r2"
753 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6
754 #define MULTILIB_ISA_DEFAULT "mips64r6"
755 #else
756 #define MULTILIB_ISA_DEFAULT "mips1"
757 #endif
758 #endif
759
760 #ifndef MIPS_ABI_DEFAULT
761 #define MIPS_ABI_DEFAULT ABI_32
762 #endif
763
764 /* Use the most portable ABI flag for the ASM specs. */
765
766 #if MIPS_ABI_DEFAULT == ABI_32
767 #define MULTILIB_ABI_DEFAULT "mabi=32"
768 #elif MIPS_ABI_DEFAULT == ABI_O64
769 #define MULTILIB_ABI_DEFAULT "mabi=o64"
770 #elif MIPS_ABI_DEFAULT == ABI_N32
771 #define MULTILIB_ABI_DEFAULT "mabi=n32"
772 #elif MIPS_ABI_DEFAULT == ABI_64
773 #define MULTILIB_ABI_DEFAULT "mabi=64"
774 #elif MIPS_ABI_DEFAULT == ABI_EABI
775 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
776 #endif
777
778 #ifndef MULTILIB_DEFAULTS
779 #define MULTILIB_DEFAULTS \
780 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
781 #endif
782
783 /* We must pass -EL to the linker by default for little endian embedded
784 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
785 linker will default to using big-endian output files. The OUTPUT_FORMAT
786 line must be in the linker script, otherwise -EB/-EL will not work. */
787
788 #ifndef ENDIAN_SPEC
789 #if TARGET_ENDIAN_DEFAULT == 0
790 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
791 #else
792 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
793 #endif
794 #endif
795
796 /* A spec condition that matches all non-mips16 -mips arguments. */
797
798 #define MIPS_ISA_LEVEL_OPTION_SPEC \
799 "mips1|mips2|mips3|mips4|mips32*|mips64*"
800
801 /* A spec condition that matches all non-mips16 architecture arguments. */
802
803 #define MIPS_ARCH_OPTION_SPEC \
804 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
805
806 /* A spec that infers a -mips argument from an -march argument. */
807
808 #define MIPS_ISA_LEVEL_SPEC \
809 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
810 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
811 %{march=mips2|march=r6000:-mips2} \
812 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
813 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
814 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
815 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
816 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
817 |march=34k*|march=74k*|march=m14k*|march=1004k* \
818 |march=interaptiv: -mips32r2} \
819 %{march=mips32r3: -mips32r3} \
820 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
821 %{march=mips32r6: -mips32r6} \
822 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
823 |march=xlr: -mips64} \
824 %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \
825 |march=octeon|march=xlp: -mips64r2} \
826 %{march=mips64r3: -mips64r3} \
827 %{march=mips64r5: -mips64r5} \
828 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
829
830 /* A spec that injects the default multilib ISA if no architecture is
831 specified. */
832
833 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
834 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
835 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
836
837 /* A spec that infers a -mhard-float or -msoft-float setting from an
838 -march argument. Note that soft-float and hard-float code are not
839 link-compatible. */
840
841 #define MIPS_ARCH_FLOAT_SPEC \
842 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
843 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
844 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
845 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
846 march=*: -mhard-float}"
847
848 /* A spec condition that matches 32-bit options. It only works if
849 MIPS_ISA_LEVEL_SPEC has been applied. */
850
851 #define MIPS_32BIT_OPTION_SPEC \
852 "mips1|mips2|mips32*|mgp32"
853
854 /* A spec condition that matches architectures should be targeted with
855 o32 FPXX for compatibility reasons. */
856 #define MIPS_FPXX_OPTION_SPEC \
857 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
858 mips64|mips64r2|mips64r3|mips64r5"
859
860 /* Infer a -msynci setting from a -mips argument, on the assumption that
861 -msynci is desired where possible. */
862 #define MIPS_ISA_SYNCI_SPEC \
863 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
864 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
865
866 /* Infer a -mnan=2008 setting from a -mips argument. */
867 #define MIPS_ISA_NAN2008_SPEC \
868 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
869 %{!msoft-float:-mnan=2008}}"
870
871 #if (MIPS_ABI_DEFAULT == ABI_O64 \
872 || MIPS_ABI_DEFAULT == ABI_N32 \
873 || MIPS_ABI_DEFAULT == ABI_64)
874 #define OPT_ARCH64 "mabi=32|mgp32:;"
875 #define OPT_ARCH32 "mabi=32|mgp32"
876 #else
877 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
878 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
879 #endif
880
881 /* Support for a compile-time default CPU, et cetera. The rules are:
882 --with-arch is ignored if -march is specified or a -mips is specified
883 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
884 --with-tune is ignored if -mtune is specified; likewise
885 --with-tune-32 and --with-tune-64.
886 --with-abi is ignored if -mabi is specified.
887 --with-float is ignored if -mhard-float or -msoft-float are
888 specified.
889 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
890 specified.
891 --with-nan is ignored if -mnan is specified.
892 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
893 specified.
894 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
895 or -mno-odd-spreg are specified.
896 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
897 specified. */
898 #define OPTION_DEFAULT_SPECS \
899 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
900 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
901 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
902 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
903 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
904 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
905 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
906 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
907 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
908 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
909 {"fp_32", "%{" OPT_ARCH32 \
910 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
911 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
912 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
913 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
914 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
915 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
916 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
917 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
918 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" }, \
919 {"compact-branches", "%{!mcompact-branches=*:-mcompact-branches=%(VALUE)}" }, \
920 {"msa", "%{!mmsa:%{!mno-msa:-m%(VALUE)}}" } \
921
922 /* A spec that infers the:
923 -mnan=2008 setting from a -mips argument,
924 -mdsp setting from a -march argument.
925 -mloongson-mmi setting from a -march argument. */
926 #define BASE_DRIVER_SELF_SPECS \
927 MIPS_ISA_NAN2008_SPEC, \
928 MIPS_ASE_DSP_SPEC, \
929 MIPS_ASE_LOONGSON_MMI_SPEC, \
930 MIPS_ASE_LOONGSON_EXT_SPEC, \
931 MIPS_ASE_MSA_SPEC
932
933
934 #define MIPS_ASE_DSP_SPEC \
935 "%{!mno-dsp: \
936 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
937 |march=interaptiv: -mdsp} \
938 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
939
940 #define MIPS_ASE_LOONGSON_MMI_SPEC \
941 "%{!mno-loongson-mmi: \
942 %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
943
944 #define MIPS_ASE_LOONGSON_EXT_SPEC \
945 "%{!mno-loongson-ext: \
946 %{march=loongson3a|march=gs464: -mloongson-ext} \
947 %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \
948 -mloongson-ext2 -mloongson-ext}}}"
949
950 #define MIPS_ASE_MSA_SPEC \
951 "%{!mno-msa: \
952 %{march=gs264e: -mmsa}}"
953
954 #define DRIVER_SELF_SPECS \
955 MIPS_ISA_LEVEL_SPEC, \
956 BASE_DRIVER_SELF_SPECS
957
958 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
959 && ISA_HAS_COND_TRAP)
960
961 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
962
963 /* True if the ABI can only work with 64-bit integer registers. We
964 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
965 otherwise floating-point registers must also be 64-bit. */
966 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
967
968 /* Likewise for 32-bit regs. */
969 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
970
971 /* True if the file format uses 64-bit symbols. At present, this is
972 only true for n64, which uses 64-bit ELF. */
973 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
974
975 /* True if symbols are 64 bits wide. This is usually determined by
976 the ABI's file format, but it can be overridden by -msym32. Note that
977 overriding the size with -msym32 changes the ABI of relocatable objects,
978 although it doesn't change the ABI of a fully-linked object. */
979 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
980 && Pmode == DImode \
981 && !TARGET_SYM32)
982
983 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
984 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
985 || ISA_MIPS4 \
986 || ISA_MIPS64 \
987 || ISA_MIPS64R2 \
988 || ISA_MIPS64R3 \
989 || ISA_MIPS64R5 \
990 || ISA_MIPS64R6)
991
992 #define ISA_HAS_JR (mips_isa_rev <= 5)
993
994 #define ISA_HAS_DELAY_SLOTS 1
995
996 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
997
998 /* ISA has branch likely instructions (e.g. mips2). */
999 /* Disable branchlikely for tx39 until compare rewrite. They haven't
1000 been generated up to this point. */
1001 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
1002
1003 /* ISA has 32 single-precision registers. */
1004 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
1005 && !TARGET_GS464) \
1006 || TARGET_FLOAT64 \
1007 || TARGET_MIPS5900)
1008
1009 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
1010 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
1011 || TARGET_MIPS5400 \
1012 || TARGET_MIPS5500 \
1013 || TARGET_MIPS5900 \
1014 || TARGET_MIPS7000 \
1015 || TARGET_MIPS9000 \
1016 || TARGET_MAD \
1017 || (mips_isa_rev >= 1 \
1018 && mips_isa_rev <= 5)) \
1019 && !TARGET_MIPS16)
1020
1021 /* ISA has a three-operand multiplication instruction. */
1022 #define ISA_HAS_DMUL3 (TARGET_64BIT \
1023 && TARGET_OCTEON \
1024 && !TARGET_MIPS16)
1025
1026 /* ISA has HI and LO registers. */
1027 #define ISA_HAS_HILO (mips_isa_rev <= 5)
1028
1029 /* ISA supports instructions DMULT and DMULTU. */
1030 #define ISA_HAS_DMULT (TARGET_64BIT \
1031 && !TARGET_MIPS5900 \
1032 && mips_isa_rev <= 5)
1033
1034 /* ISA supports instructions MULT and MULTU. */
1035 #define ISA_HAS_MULT (mips_isa_rev <= 5)
1036
1037 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
1038 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
1039
1040 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
1041 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
1042
1043 /* For Loongson, it is preferable to use the Loongson-specific division and
1044 modulo instructions instead of the regular (D)DIV(U) instruction,
1045 because the former are faster and can also have the effect of reducing
1046 code size. */
1047 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
1048 || TARGET_GS464) \
1049 && !TARGET_MIPS16)
1050
1051 /* ISA supports instructions DDIV and DDIVU. */
1052 #define ISA_HAS_DDIV (TARGET_64BIT \
1053 && !TARGET_MIPS5900 \
1054 && !ISA_AVOID_DIV_HILO \
1055 && mips_isa_rev <= 5)
1056
1057 /* ISA supports instructions DIV and DIVU.
1058 This is always true, but the macro is needed for ISA_HAS_<D>DIV
1059 in mips.md. */
1060 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
1061 && mips_isa_rev <= 5)
1062
1063 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
1064 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
1065
1066 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1067 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1068
1069 /* ISA has the floating-point conditional move instructions introduced
1070 in mips4. */
1071 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1072 || (mips_isa_rev >= 1 \
1073 && mips_isa_rev <= 5)) \
1074 && !TARGET_MIPS5500 \
1075 && !TARGET_MIPS16)
1076
1077 /* ISA has the integer conditional move instructions introduced in mips4 and
1078 ST Loongson 2E/2F. */
1079 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1080 || TARGET_MIPS5900 \
1081 || TARGET_LOONGSON_2EF)
1082
1083 /* ISA has LDC1 and SDC1. */
1084 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1085 && !TARGET_MIPS5900 \
1086 && !TARGET_MIPS16)
1087
1088 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1089 branch on CC, and move (both FP and non-FP) on CC. */
1090 #define ISA_HAS_8CC (ISA_MIPS4 \
1091 || (mips_isa_rev >= 1 \
1092 && mips_isa_rev <= 5))
1093
1094 /* ISA has the FP condition code instructions that store the flag in an
1095 FP register. */
1096 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1097
1098 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1099
1100 /* This is a catch all for other mips4 instructions: indexed load, the
1101 FP madd and msub instructions, and the FP recip and recip sqrt
1102 instructions. Note that this macro should only be used by other
1103 ISA_HAS_* macros. */
1104 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1105 || ISA_MIPS64 \
1106 || (mips_isa_rev >= 2 \
1107 && mips_isa_rev <= 5)) \
1108 && !TARGET_MIPS16)
1109
1110 /* ISA has floating-point indexed load and store instructions
1111 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1112 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1113 && mips_lxc1_sxc1)
1114
1115 /* ISA has paired-single instructions. */
1116 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1117 || (mips_isa_rev >= 2 \
1118 && mips_isa_rev <= 5)) \
1119 && !TARGET_OCTEON)
1120
1121 /* ISA has conditional trap instructions. */
1122 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1123 && !TARGET_MIPS16)
1124
1125 /* ISA has conditional trap with immediate instructions. */
1126 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1127 && mips_isa_rev <= 5 \
1128 && !TARGET_MIPS16)
1129
1130 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1131 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1132 && mips_isa_rev <= 5)
1133
1134 /* Integer multiply-accumulate instructions should be generated. */
1135 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1136
1137 /* ISA has 4 operand fused madd instructions of the form
1138 'd = [+-] (a * b [+-] c)'. */
1139 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1140 && (TARGET_MIPS8000 \
1141 || TARGET_GS464 \
1142 || TARGET_GS464E \
1143 || TARGET_GS264E))
1144
1145 /* ISA has 4 operand unfused madd instructions of the form
1146 'd = [+-] (a * b [+-] c)'. */
1147 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1148 && ISA_HAS_FP4 \
1149 && !TARGET_MIPS8000 \
1150 && !TARGET_GS464 \
1151 && !TARGET_GS464E \
1152 && !TARGET_GS264E)
1153
1154 /* ISA has 3 operand r6 fused madd instructions of the form
1155 'c = c [+-] (a * b)'. */
1156 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1157
1158 /* ISA has 3 operand loongson fused madd instructions of the form
1159 'c = [+-] (a * b [+-] c)'. */
1160 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1161
1162 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1163 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1164 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1165 this restriction to the MIPS IV ISA too. */
1166 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1167 (((ISA_HAS_FP4 \
1168 && ((MODE) == SFmode \
1169 || ((TARGET_FLOAT64 \
1170 || mips_isa_rev >= 2) \
1171 && (MODE) == DFmode))) \
1172 || (((MODE) == SFmode \
1173 || (MODE) == DFmode) \
1174 && (mips_isa_rev >= 6)) \
1175 || (TARGET_SB1 \
1176 && (MODE) == V2SFmode)) \
1177 && !TARGET_MIPS16)
1178
1179 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1180
1181 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1182
1183 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1184
1185 /* ISA has count leading zeroes/ones instruction (not implemented). */
1186 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1187
1188 /* ISA has count trailing zeroes/ones instruction. */
1189 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
1190
1191 /* ISA has three operand multiply instructions that put
1192 the high part in an accumulator: mulhi or mulhiu. */
1193 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1194 || TARGET_MIPS5500 \
1195 || TARGET_SR71K) \
1196 && !TARGET_MIPS16)
1197
1198 /* ISA has three operand multiply instructions that negate the
1199 result and put the result in an accumulator. */
1200 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1201 || TARGET_MIPS5500 \
1202 || TARGET_SR71K) \
1203 && !TARGET_MIPS16)
1204
1205 /* ISA has three operand multiply instructions that subtract the
1206 result from a 4th operand and put the result in an accumulator. */
1207 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1208 || TARGET_MIPS5500 \
1209 || TARGET_SR71K) \
1210 && !TARGET_MIPS16)
1211
1212 /* ISA has three operand multiply instructions that add the result
1213 to a 4th operand and put the result in an accumulator. */
1214 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1215 || TARGET_MIPS4130 \
1216 || TARGET_MIPS5400 \
1217 || TARGET_MIPS5500 \
1218 || TARGET_SR71K) \
1219 && !TARGET_MIPS16)
1220
1221 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1222 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1223 || TARGET_MIPS4130) \
1224 && !TARGET_MIPS16)
1225
1226 /* ISA has the "ror" (rotate right) instructions. */
1227 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1228 || TARGET_MIPS5400 \
1229 || TARGET_MIPS5500 \
1230 || TARGET_SR71K \
1231 || TARGET_SMARTMIPS) \
1232 && !TARGET_MIPS16)
1233
1234 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1235 64-bit targets also provide DSBH and DSHD. */
1236 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1237
1238 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1239 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1240 || TARGET_LOONGSON_2EF \
1241 || TARGET_MIPS5900 \
1242 || mips_isa_rev >= 1) \
1243 && !TARGET_MIPS16)
1244
1245 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1246 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1247
1248 /* ISA has data indexed prefetch instructions. This controls use of
1249 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1250 (prefx is a cop1x instruction, so can only be used if FP is
1251 enabled.) */
1252 #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \
1253 || TARGET_LOONGSON_EXT \
1254 || TARGET_LOONGSON_EXT2)
1255
1256 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1257 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1258 also requires TARGET_DOUBLE_FLOAT. */
1259 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1260
1261 /* ISA includes the MIPS32r2 seb and seh instructions. */
1262 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1263
1264 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1265 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1266
1267 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1268 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1269 && mips_isa_rev >= 2)
1270
1271 /* ISA has lwxs instruction (load w/scaled index address. */
1272 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1273 && !TARGET_MIPS16)
1274
1275 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1276 #define ISA_HAS_LBX (TARGET_OCTEON2)
1277 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1278 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1279 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1280 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1281 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1282 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1283 && TARGET_64BIT)
1284
1285 /* The DSP ASE is available. */
1286 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1287
1288 /* Revision 2 of the DSP ASE is available. */
1289 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1290
1291 /* The MSA ASE is available. */
1292 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1293
1294 /* True if the result of a load is not available to the next instruction.
1295 A nop will then be needed between instructions like "lw $4,..."
1296 and "addiu $4,$4,1". */
1297 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1298 && !TARGET_MIPS3900 \
1299 && !TARGET_MIPS5900 \
1300 && !TARGET_MIPS16 \
1301 && !TARGET_MICROMIPS)
1302
1303 /* Likewise mtc1 and mfc1. */
1304 #define ISA_HAS_XFER_DELAY (mips_isa <= MIPS_ISA_MIPS3 \
1305 && !TARGET_MIPS5900 \
1306 && !TARGET_LOONGSON_2EF)
1307
1308 /* Likewise floating-point comparisons. */
1309 #define ISA_HAS_FCMP_DELAY (mips_isa <= MIPS_ISA_MIPS3 \
1310 && !TARGET_MIPS5900 \
1311 && !TARGET_LOONGSON_2EF)
1312
1313 /* True if mflo and mfhi can be immediately followed by instructions
1314 which write to the HI and LO registers.
1315
1316 According to MIPS specifications, MIPS ISAs I, II, and III need
1317 (at least) two instructions between the reads of HI/LO and
1318 instructions which write them, and later ISAs do not. Contradicting
1319 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1320 the UM for the NEC Vr5000) document needing the instructions between
1321 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1322 MIPS64 and later ISAs to have the interlocks, plus any specific
1323 earlier-ISA CPUs for which CPU documentation declares that the
1324 instructions are really interlocked. */
1325 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1326 || TARGET_MIPS5500 \
1327 || TARGET_MIPS5900 \
1328 || TARGET_LOONGSON_2EF)
1329
1330 /* ISA includes synci, jr.hb and jalr.hb. */
1331 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1332
1333 /* ISA includes sync. */
1334 #define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1335 #define GENERATE_SYNC \
1336 (target_flags_explicit & MASK_LLSC \
1337 ? TARGET_LLSC && !TARGET_MIPS16 \
1338 : ISA_HAS_SYNC)
1339
1340 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1341 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1342 instructions. */
1343 #define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1344 #define GENERATE_LL_SC \
1345 (target_flags_explicit & MASK_LLSC \
1346 ? TARGET_LLSC && !TARGET_MIPS16 \
1347 : ISA_HAS_LL_SC)
1348
1349 #define ISA_HAS_SWAP (TARGET_XLP)
1350 #define ISA_HAS_LDADD (TARGET_XLP)
1351
1352 /* ISA includes the baddu instruction. */
1353 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1354
1355 /* ISA includes the bbit* instructions. */
1356 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1357
1358 /* ISA includes the cins instruction. */
1359 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1360
1361 /* ISA includes the exts instruction. */
1362 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1363
1364 /* ISA includes the seq and sne instructions. */
1365 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1366
1367 /* ISA includes the pop instruction. */
1368 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1369
1370 /* The CACHE instruction is available in non-MIPS16 code. */
1371 #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3)
1372
1373 /* The CACHE instruction is available. */
1374 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1375
1376 /* Tell collect what flags to pass to nm. */
1377 #ifndef NM_FLAGS
1378 #define NM_FLAGS "-Bn"
1379 #endif
1380
1381
1382 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1383 the assembler. It may be overridden by subtargets.
1384
1385 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1386 COFF debugging info. */
1387
1388 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1389 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1390 %{g} %{g0} %{g1} %{g2} %{g3} \
1391 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3}"
1392 #endif
1393
1394 /* FP_ASM_SPEC represents the floating-point options that must be passed
1395 to the assembler when FPXX support exists. Prior to that point the
1396 assembler could accept the options but were not required for
1397 correctness. We only add the options when absolutely necessary
1398 because passing -msoft-float to the assembler will cause it to reject
1399 all hard-float instructions which may require some user code to be
1400 updated. */
1401
1402 #ifdef HAVE_AS_DOT_MODULE
1403 #define FP_ASM_SPEC "\
1404 %{mhard-float} %{msoft-float} \
1405 %{msingle-float} %{mdouble-float}"
1406 #else
1407 #define FP_ASM_SPEC
1408 #endif
1409
1410 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1411 overridden by subtargets. */
1412
1413 #ifndef SUBTARGET_ASM_SPEC
1414 #define SUBTARGET_ASM_SPEC ""
1415 #endif
1416
1417 #undef ASM_SPEC
1418 #define ASM_SPEC "\
1419 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1420 %{mips32*} %{mips64*} \
1421 %{mips16} %{mno-mips16:-no-mips16} \
1422 %{mmicromips} %{mno-micromips} \
1423 %{mips3d} %{mno-mips3d:-no-mips3d} \
1424 %{mdmx} %{mno-mdmx:-no-mdmx} \
1425 %{mdsp} %{mno-dsp} \
1426 %{mdspr2} %{mno-dspr2} \
1427 %{mmcu} %{mno-mcu} \
1428 %{meva} %{mno-eva} \
1429 %{mvirt} %{mno-virt} \
1430 %{mxpa} %{mno-xpa} \
1431 %{mcrc} %{mno-crc} \
1432 %{mginv} %{mno-ginv} \
1433 %{mmsa} %{mno-msa} \
1434 %{mloongson-mmi} %{mno-loongson-mmi} \
1435 %{mloongson-ext} %{mno-loongson-ext} \
1436 %{mloongson-ext2} %{mno-loongson-ext2} \
1437 %{msmartmips} %{mno-smartmips} \
1438 %{mmt} %{mno-mt} \
1439 %{mfix-r5900} %{mno-fix-r5900} \
1440 %{mfix-rm7000} %{mno-fix-rm7000} \
1441 %{mfix-vr4120} %{mfix-vr4130} \
1442 %{mfix-24k} \
1443 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1444 %(subtarget_asm_debugging_spec) \
1445 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1446 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1447 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1448 %{modd-spreg} %{mno-odd-spreg} \
1449 %{mshared} %{mno-shared} \
1450 %{msym32} %{mno-sym32} \
1451 %{mtune=*}" \
1452 FP_ASM_SPEC "\
1453 %(subtarget_asm_spec)"
1454
1455 /* Extra switches sometimes passed to the linker. */
1456
1457 #ifndef LINK_SPEC
1458 #define LINK_SPEC "\
1459 %(endian_spec) \
1460 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1461 %{shared}"
1462 #endif /* LINK_SPEC defined */
1463
1464
1465 /* Specs for the compiler proper */
1466
1467 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1468 overridden by subtargets. */
1469 #ifndef SUBTARGET_CC1_SPEC
1470 #define SUBTARGET_CC1_SPEC ""
1471 #endif
1472
1473 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1474
1475 #undef CC1_SPEC
1476 #define CC1_SPEC "\
1477 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1478 %(subtarget_cc1_spec)"
1479
1480 /* Preprocessor specs. */
1481
1482 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1483 overridden by subtargets. */
1484 #ifndef SUBTARGET_CPP_SPEC
1485 #define SUBTARGET_CPP_SPEC ""
1486 #endif
1487
1488 #define CPP_SPEC "%(subtarget_cpp_spec)"
1489
1490 /* This macro defines names of additional specifications to put in the specs
1491 that can be used in various specifications like CC1_SPEC. Its definition
1492 is an initializer with a subgrouping for each command option.
1493
1494 Each subgrouping contains a string constant, that defines the
1495 specification name, and a string constant that used by the GCC driver
1496 program.
1497
1498 Do not define this macro if it does not need to do anything. */
1499
1500 #define EXTRA_SPECS \
1501 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1502 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1503 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1504 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1505 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1506 { "endian_spec", ENDIAN_SPEC }, \
1507 SUBTARGET_EXTRA_SPECS
1508
1509 #ifndef SUBTARGET_EXTRA_SPECS
1510 #define SUBTARGET_EXTRA_SPECS
1511 #endif
1512
1513 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1514
1515 #ifndef PREFERRED_DEBUGGING_TYPE
1516 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1517 #endif
1518
1519 /* The size of DWARF addresses should be the same as the size of symbols
1520 in the target file format. They shouldn't depend on things like -msym32,
1521 because many DWARF consumers do not allow the mixture of address sizes
1522 that one would then get from linking -msym32 code with -msym64 code.
1523
1524 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1525 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1526 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1527
1528 /* By default, turn on GDB extensions. */
1529 #define DEFAULT_GDB_EXTENSIONS 1
1530
1531 /* Registers may have a prefix which can be ignored when matching
1532 user asm and register definitions. */
1533 #ifndef REGISTER_PREFIX
1534 #define REGISTER_PREFIX "$"
1535 #endif
1536
1537 /* Local compiler-generated symbols must have a prefix that the assembler
1538 understands. By default, this is $, although some targets (e.g.,
1539 NetBSD-ELF) need to override this. */
1540
1541 #ifndef LOCAL_LABEL_PREFIX
1542 #define LOCAL_LABEL_PREFIX "$"
1543 #endif
1544
1545 /* By default on the mips, external symbols do not have an underscore
1546 prepended, but some targets (e.g., NetBSD) require this. */
1547
1548 #ifndef USER_LABEL_PREFIX
1549 #define USER_LABEL_PREFIX ""
1550 #endif
1551
1552 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1553 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1554
1555 /* The DWARF 2 CFA column which tracks the return address. */
1556 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1557
1558 /* Before the prologue, RA lives in r31. */
1559 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1560
1561 /* Describe how we implement __builtin_eh_return. */
1562 #define EH_RETURN_DATA_REGNO(N) \
1563 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1564
1565 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1566
1567 #define EH_USES(N) mips_eh_uses (N)
1568
1569 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1570 The default for this in 64-bit mode is 8, which causes problems with
1571 SFmode register saves. */
1572 #define DWARF_CIE_DATA_ALIGNMENT -4
1573
1574 /* Correct the offset of automatic variables and arguments. Note that
1575 the MIPS debug format wants all automatic variables and arguments
1576 to be in terms of the virtual frame pointer (stack pointer before
1577 any adjustment in the function), while the MIPS 3.0 linker wants
1578 the frame pointer to be the stack pointer after the initial
1579 adjustment. */
1580
1581 #define DEBUGGER_AUTO_OFFSET(X) \
1582 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1583 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1584 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1585
1586 /* Target machine storage layout */
1587
1588 #define BITS_BIG_ENDIAN 0
1589 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1590 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1591
1592 #define MAX_BITS_PER_WORD 64
1593
1594 /* Width of a word, in units (bytes). */
1595 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1596 #ifndef IN_LIBGCC2
1597 #define MIN_UNITS_PER_WORD 4
1598 #endif
1599
1600 /* Width of a MSA vector register in bytes. */
1601 #define UNITS_PER_MSA_REG 16
1602 /* Width of a MSA vector register in bits. */
1603 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1604
1605 /* For MIPS, width of a floating point register. */
1606 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1607
1608 /* The number of consecutive floating-point registers needed to store the
1609 largest format supported by the FPU. */
1610 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1611
1612 /* The number of consecutive floating-point registers needed to store the
1613 smallest format supported by the FPU. */
1614 #define MIN_FPRS_PER_FMT \
1615 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1616
1617 /* The largest size of value that can be held in floating-point
1618 registers and moved with a single instruction. */
1619 #define UNITS_PER_HWFPVALUE \
1620 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1621
1622 /* The largest size of value that can be held in floating-point
1623 registers. */
1624 #define UNITS_PER_FPVALUE \
1625 (TARGET_SOFT_FLOAT_ABI ? 0 \
1626 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1627 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1628
1629 /* The number of bytes in a double. */
1630 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1631
1632 /* Set the sizes of the core types. */
1633 #define SHORT_TYPE_SIZE 16
1634 #define INT_TYPE_SIZE 32
1635 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1636 #define LONG_LONG_TYPE_SIZE 64
1637
1638 #define FLOAT_TYPE_SIZE 32
1639 #define DOUBLE_TYPE_SIZE 64
1640 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1641
1642 /* Define the sizes of fixed-point types. */
1643 #define SHORT_FRACT_TYPE_SIZE 8
1644 #define FRACT_TYPE_SIZE 16
1645 #define LONG_FRACT_TYPE_SIZE 32
1646 #define LONG_LONG_FRACT_TYPE_SIZE 64
1647
1648 #define SHORT_ACCUM_TYPE_SIZE 16
1649 #define ACCUM_TYPE_SIZE 32
1650 #define LONG_ACCUM_TYPE_SIZE 64
1651 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1652 doesn't support 128-bit integers for MIPS32 currently. */
1653 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1654
1655 /* long double is not a fixed mode, but the idea is that, if we
1656 support long double, we also want a 128-bit integer type. */
1657 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1658
1659 /* Width in bits of a pointer. */
1660 #ifndef POINTER_SIZE
1661 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1662 #endif
1663
1664 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1665 #define PARM_BOUNDARY BITS_PER_WORD
1666
1667 /* Allocation boundary (in *bits*) for the code of a function. */
1668 #define FUNCTION_BOUNDARY 32
1669
1670 /* Alignment of field after `int : 0' in a structure. */
1671 #define EMPTY_FIELD_BOUNDARY 32
1672
1673 /* Every structure's size must be a multiple of this. */
1674 /* 8 is observed right on a DECstation and on riscos 4.02. */
1675 #define STRUCTURE_SIZE_BOUNDARY 8
1676
1677 /* There is no point aligning anything to a rounder boundary than
1678 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1679 BITS_PER_MSA_REG. */
1680 #define BIGGEST_ALIGNMENT \
1681 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
1682
1683 /* All accesses must be aligned. */
1684 #define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS)
1685
1686 /* Define this if you wish to imitate the way many other C compilers
1687 handle alignment of bitfields and the structures that contain
1688 them.
1689
1690 The behavior is that the type written for a bit-field (`int',
1691 `short', or other integer type) imposes an alignment for the
1692 entire structure, as if the structure really did contain an
1693 ordinary field of that type. In addition, the bit-field is placed
1694 within the structure so that it would fit within such a field,
1695 not crossing a boundary for it.
1696
1697 Thus, on most machines, a bit-field whose type is written as `int'
1698 would not cross a four-byte boundary, and would force four-byte
1699 alignment for the whole structure. (The alignment used may not
1700 be four bytes; it is controlled by the other alignment
1701 parameters.)
1702
1703 If the macro is defined, its definition should be a C expression;
1704 a nonzero value for the expression enables this behavior. */
1705
1706 #define PCC_BITFIELD_TYPE_MATTERS 1
1707
1708 /* If defined, a C expression to compute the alignment for a static
1709 variable. TYPE is the data type, and ALIGN is the alignment that
1710 the object would ordinarily have. The value of this macro is used
1711 instead of that alignment to align the object.
1712
1713 If this macro is not defined, then ALIGN is used.
1714
1715 One use of this macro is to increase alignment of medium-size
1716 data to make it all fit in fewer cache lines. Another is to
1717 cause character arrays to be word-aligned so that `strcpy' calls
1718 that copy constants to character arrays can be done inline. */
1719
1720 #undef DATA_ALIGNMENT
1721 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1722 ((((ALIGN) < BITS_PER_WORD) \
1723 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1724 || TREE_CODE (TYPE) == UNION_TYPE \
1725 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1726
1727 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1728 character arrays to be word-aligned so that `strcpy' calls that copy
1729 constants to character arrays can be done inline, and 'strcmp' can be
1730 optimised to use word loads. */
1731 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1732 DATA_ALIGNMENT (TYPE, ALIGN)
1733
1734 #define PAD_VARARGS_DOWN \
1735 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1736
1737 /* Define if operations between registers always perform the operation
1738 on the full register even if a narrower mode is specified. */
1739 #define WORD_REGISTER_OPERATIONS 1
1740
1741 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1742 moves. All other references are zero extended. */
1743 #define LOAD_EXTEND_OP(MODE) \
1744 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1745 ? SIGN_EXTEND : ZERO_EXTEND)
1746
1747 /* Define this macro if it is advisable to hold scalars in registers
1748 in a wider mode than that declared by the program. In such cases,
1749 the value is constrained to be within the bounds of the declared
1750 type, but kept valid in the wider mode. The signedness of the
1751 extension may differ from that of the type. */
1752
1753 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1754 if (GET_MODE_CLASS (MODE) == MODE_INT \
1755 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1756 { \
1757 if ((MODE) == SImode) \
1758 (UNSIGNEDP) = 0; \
1759 (MODE) = Pmode; \
1760 }
1761
1762 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1763 Extensions of pointers to word_mode must be signed. */
1764 #define POINTERS_EXTEND_UNSIGNED false
1765
1766 /* Define if loading short immediate values into registers sign extends. */
1767 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1768
1769 /* The [d]clz instructions have the natural values at 0. */
1770
1771 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1772 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1773
1774 /* Standard register usage. */
1775
1776 /* Number of hardware registers. We have:
1777
1778 - 32 integer registers
1779 - 32 floating point registers
1780 - 8 condition code registers
1781 - 2 accumulator registers (hi and lo)
1782 - 32 registers each for coprocessors 0, 2 and 3
1783 - 4 fake registers:
1784 - ARG_POINTER_REGNUM
1785 - FRAME_POINTER_REGNUM
1786 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1787 - CPRESTORE_SLOT_REGNUM
1788 - 2 dummy entries that were used at various times in the past.
1789 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1790 - 6 DSP control registers */
1791
1792 #define FIRST_PSEUDO_REGISTER 188
1793
1794 /* By default, fix the kernel registers ($26 and $27), the global
1795 pointer ($28) and the stack pointer ($29). This can change
1796 depending on the command-line options.
1797
1798 Regarding coprocessor registers: without evidence to the contrary,
1799 it's best to assume that each coprocessor register has a unique
1800 use. This can be overridden, in, e.g., mips_option_override or
1801 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1802 inappropriate for a particular target. */
1803
1804 #define FIXED_REGISTERS \
1805 { \
1806 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1807 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1809 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1810 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1811 /* COP0 registers */ \
1812 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1813 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1814 /* COP2 registers */ \
1815 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1816 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1817 /* COP3 registers */ \
1818 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1819 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1820 /* 6 DSP accumulator registers & 6 control registers */ \
1821 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1822 }
1823
1824
1825 /* Set up this array for o32 by default.
1826
1827 Note that we don't mark $31 as a call-clobbered register. The idea is
1828 that it's really the call instructions themselves which clobber $31.
1829 We don't care what the called function does with it afterwards.
1830
1831 This approach makes it easier to implement sibcalls. Unlike normal
1832 calls, sibcalls don't clobber $31, so the register reaches the
1833 called function in tact. EPILOGUE_USES says that $31 is useful
1834 to the called function. */
1835
1836 #define CALL_REALLY_USED_REGISTERS \
1837 { /* General registers. */ \
1838 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1839 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1840 /* Floating-point registers. */ \
1841 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1842 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1843 /* Others. */ \
1844 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1845 /* COP0 registers */ \
1846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1847 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1848 /* COP2 registers */ \
1849 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1850 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1851 /* COP3 registers */ \
1852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1854 /* 6 DSP accumulator registers & 6 control registers */ \
1855 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1856 }
1857
1858 /* Internal macros to classify a register number as to whether it's a
1859 general purpose register, a floating point register, a
1860 multiply/divide register, or a status register. */
1861
1862 #define GP_REG_FIRST 0
1863 #define GP_REG_LAST 31
1864 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1865 #define K0_REG_NUM (GP_REG_FIRST + 26)
1866 #define K1_REG_NUM (GP_REG_FIRST + 27)
1867 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1868
1869 #define FP_REG_FIRST 32
1870 #define FP_REG_LAST 63
1871 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1872
1873 #define MD_REG_FIRST 64
1874 #define MD_REG_LAST 65
1875 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1876
1877 #define MSA_REG_FIRST FP_REG_FIRST
1878 #define MSA_REG_LAST FP_REG_LAST
1879 #define MSA_REG_NUM FP_REG_NUM
1880
1881 /* The DWARF 2 CFA column which tracks the return address from a
1882 signal handler context. This means that to maintain backwards
1883 compatibility, no hard register can be assigned this column if it
1884 would need to be handled by the DWARF unwinder. */
1885 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1886
1887 #define ST_REG_FIRST 67
1888 #define ST_REG_LAST 74
1889 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1890
1891
1892 /* FIXME: renumber. */
1893 #define COP0_REG_FIRST 80
1894 #define COP0_REG_LAST 111
1895 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1896
1897 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1898 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1899 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1900
1901 #define COP2_REG_FIRST 112
1902 #define COP2_REG_LAST 143
1903 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1904
1905 #define COP3_REG_FIRST 144
1906 #define COP3_REG_LAST 175
1907 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1908
1909 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1910 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1911 #define ALL_COP_REG_LAST COP3_REG_LAST
1912 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1913
1914 #define DSP_ACC_REG_FIRST 176
1915 #define DSP_ACC_REG_LAST 181
1916 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1917
1918 #define AT_REGNUM (GP_REG_FIRST + 1)
1919 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1920 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1921
1922 /* A few bitfield locations for the coprocessor registers. */
1923 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1924 the cause register for the EIC interrupt mode. */
1925 #define CAUSE_IPL 10
1926 /* COP1 Enable is at bit 29 of the status register. */
1927 #define SR_COP1 29
1928 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1929 #define SR_IPL 10
1930 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1931 register. */
1932 #define SR_IM0 8
1933 /* Exception Level is at bit 1 of the status register. */
1934 #define SR_EXL 1
1935 /* Interrupt Enable is at bit 0 of the status register. */
1936 #define SR_IE 0
1937
1938 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1939 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1940 should be used instead. */
1941 #define FPSW_REGNUM ST_REG_FIRST
1942
1943 #define GP_REG_P(REGNO) \
1944 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1945 #define M16_REG_P(REGNO) \
1946 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1947 #define M16STORE_REG_P(REGNO) \
1948 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1949 #define FP_REG_P(REGNO) \
1950 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1951 #define MD_REG_P(REGNO) \
1952 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1953 #define ST_REG_P(REGNO) \
1954 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1955 #define COP0_REG_P(REGNO) \
1956 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1957 #define COP2_REG_P(REGNO) \
1958 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1959 #define COP3_REG_P(REGNO) \
1960 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1961 #define ALL_COP_REG_P(REGNO) \
1962 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1963 /* Test if REGNO is one of the 6 new DSP accumulators. */
1964 #define DSP_ACC_REG_P(REGNO) \
1965 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1966 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1967 #define ACC_REG_P(REGNO) \
1968 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1969 #define MSA_REG_P(REGNO) \
1970 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
1971
1972 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1973 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
1974
1975 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1976 to initialize the mips16 gp pseudo register. */
1977 #define CONST_GP_P(X) \
1978 (GET_CODE (X) == CONST \
1979 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1980 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1981
1982 /* Return coprocessor number from register number. */
1983
1984 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1985 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1986 : COP3_REG_P (REGNO) ? '3' : '?')
1987
1988
1989 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1990 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
1991
1992 /* Select a register mode required for caller save of hard regno REGNO. */
1993 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1994 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1995
1996 /* Register to use for pushing function arguments. */
1997 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1998
1999 /* These two registers don't really exist: they get eliminated to either
2000 the stack or hard frame pointer. */
2001 #define ARG_POINTER_REGNUM 77
2002 #define FRAME_POINTER_REGNUM 78
2003
2004 /* $30 is not available on the mips16, so we use $17 as the frame
2005 pointer. */
2006 #define HARD_FRAME_POINTER_REGNUM \
2007 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
2008
2009 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
2010 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
2011
2012 /* Register in which static-chain is passed to a function. */
2013 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
2014
2015 /* Registers used as temporaries in prologue/epilogue code:
2016
2017 - If a MIPS16 PIC function needs access to _gp, it first loads
2018 the value into MIPS16_PIC_TEMP and then copies it to $gp.
2019
2020 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
2021 register. The register must not conflict with MIPS16_PIC_TEMP.
2022
2023 - If we aren't generating MIPS16 code, the prologue can also use
2024 MIPS_PROLOGUE_TEMP2 as a general temporary register.
2025
2026 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
2027 register.
2028
2029 If we're generating MIPS16 code, these registers must come from the
2030 core set of 8. The prologue registers mustn't conflict with any
2031 incoming arguments, the static chain pointer, or the frame pointer.
2032 The epilogue temporary mustn't conflict with the return registers,
2033 the PIC call register ($25), the frame pointer, the EH stack adjustment,
2034 or the EH data registers.
2035
2036 If we're generating interrupt handlers, we use K0 as a temporary register
2037 in prologue/epilogue code. */
2038
2039 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
2040 #define MIPS_PROLOGUE_TEMP_REGNUM \
2041 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
2042 #define MIPS_PROLOGUE_TEMP2_REGNUM \
2043 (TARGET_MIPS16 \
2044 ? (gcc_unreachable (), INVALID_REGNUM) \
2045 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2046 #define MIPS_EPILOGUE_TEMP_REGNUM \
2047 (cfun->machine->interrupt_handler_p \
2048 ? K0_REG_NUM \
2049 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2050
2051 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2052 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2053 #define MIPS_PROLOGUE_TEMP2(MODE) \
2054 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2055 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2056
2057 /* Define this macro if it is as good or better to call a constant
2058 function address than to call an address kept in a register. */
2059 #define NO_FUNCTION_CSE 1
2060
2061 /* The ABI-defined global pointer. Sometimes we use a different
2062 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
2063 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
2064
2065 /* We normally use $28 as the global pointer. However, when generating
2066 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2067 register instead. They can then avoid saving and restoring $28
2068 and perhaps avoid using a frame at all.
2069
2070 When a leaf function uses something other than $28, mips_expand_prologue
2071 will modify pic_offset_table_rtx in place. Take the register number
2072 from there after reload. */
2073 #define PIC_OFFSET_TABLE_REGNUM \
2074 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2075
2076 /* Define the classes of registers for register constraints in the
2077 machine description. Also define ranges of constants.
2078
2079 One of the classes must always be named ALL_REGS and include all hard regs.
2080 If there is more than one class, another class must be named NO_REGS
2081 and contain no registers.
2082
2083 The name GENERAL_REGS must be the name of a class (or an alias for
2084 another name such as ALL_REGS). This is the class of registers
2085 that is allowed by "g" or "r" in a register constraint.
2086 Also, registers outside this class are allocated only when
2087 instructions express preferences for them.
2088
2089 The classes must be numbered in nondecreasing order; that is,
2090 a larger-numbered class must never be contained completely
2091 in a smaller-numbered class.
2092
2093 For any two classes, it is very desirable that there be another
2094 class that represents their union. */
2095
2096 enum reg_class
2097 {
2098 NO_REGS, /* no registers in set */
2099 M16_STORE_REGS, /* microMIPS store registers */
2100 M16_REGS, /* mips16 directly accessible registers */
2101 M16_SP_REGS, /* mips16 + $sp */
2102 T_REG, /* mips16 T register ($24) */
2103 M16_T_REGS, /* mips16 registers plus T register */
2104 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2105 V1_REG, /* Register $v1 ($3) used for TLS access. */
2106 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2107 LEA_REGS, /* Every GPR except $25 */
2108 GR_REGS, /* integer registers */
2109 FP_REGS, /* floating point registers */
2110 MD0_REG, /* first multiply/divide register */
2111 MD1_REG, /* second multiply/divide register */
2112 MD_REGS, /* multiply/divide registers (hi/lo) */
2113 COP0_REGS, /* generic coprocessor classes */
2114 COP2_REGS,
2115 COP3_REGS,
2116 ST_REGS, /* status registers (fp status) */
2117 DSP_ACC_REGS, /* DSP accumulator registers */
2118 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2119 FRAME_REGS, /* $arg and $frame */
2120 GR_AND_MD0_REGS, /* union classes */
2121 GR_AND_MD1_REGS,
2122 GR_AND_MD_REGS,
2123 GR_AND_ACC_REGS,
2124 ALL_REGS, /* all registers */
2125 LIM_REG_CLASSES /* max value + 1 */
2126 };
2127
2128 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2129
2130 #define GENERAL_REGS GR_REGS
2131
2132 /* An initializer containing the names of the register classes as C
2133 string constants. These names are used in writing some of the
2134 debugging dumps. */
2135
2136 #define REG_CLASS_NAMES \
2137 { \
2138 "NO_REGS", \
2139 "M16_STORE_REGS", \
2140 "M16_REGS", \
2141 "M16_SP_REGS", \
2142 "T_REG", \
2143 "M16_T_REGS", \
2144 "PIC_FN_ADDR_REG", \
2145 "V1_REG", \
2146 "SPILL_REGS", \
2147 "LEA_REGS", \
2148 "GR_REGS", \
2149 "FP_REGS", \
2150 "MD0_REG", \
2151 "MD1_REG", \
2152 "MD_REGS", \
2153 /* coprocessor registers */ \
2154 "COP0_REGS", \
2155 "COP2_REGS", \
2156 "COP3_REGS", \
2157 "ST_REGS", \
2158 "DSP_ACC_REGS", \
2159 "ACC_REGS", \
2160 "FRAME_REGS", \
2161 "GR_AND_MD0_REGS", \
2162 "GR_AND_MD1_REGS", \
2163 "GR_AND_MD_REGS", \
2164 "GR_AND_ACC_REGS", \
2165 "ALL_REGS" \
2166 }
2167
2168 /* An initializer containing the contents of the register classes,
2169 as integers which are bit masks. The Nth integer specifies the
2170 contents of class N. The way the integer MASK is interpreted is
2171 that register R is in the class if `MASK & (1 << R)' is 1.
2172
2173 When the machine has more than 32 registers, an integer does not
2174 suffice. Then the integers are replaced by sub-initializers,
2175 braced groupings containing several integers. Each
2176 sub-initializer must be suitable as an initializer for the type
2177 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2178
2179 #define REG_CLASS_CONTENTS \
2180 { \
2181 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2182 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2183 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2184 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2185 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2186 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2187 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2188 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2189 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2190 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2191 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2192 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2193 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2194 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2195 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2196 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2197 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2198 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2199 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2200 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2201 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2202 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2203 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2204 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2205 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2206 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2207 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2208 }
2209
2210
2211 /* A C expression whose value is a register class containing hard
2212 register REGNO. In general there is more that one such class;
2213 choose a class which is "minimal", meaning that no smaller class
2214 also contains the register. */
2215
2216 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2217
2218 /* A macro whose definition is the name of the class to which a
2219 valid base register must belong. A base register is one used in
2220 an address which is the register value plus a displacement. */
2221
2222 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2223
2224 /* A macro whose definition is the name of the class to which a
2225 valid index register must belong. An index register is one used
2226 in an address where its value is either multiplied by a scale
2227 factor or added to another register (as well as added to a
2228 displacement). */
2229
2230 #define INDEX_REG_CLASS NO_REGS
2231
2232 /* We generally want to put call-clobbered registers ahead of
2233 call-saved ones. (IRA expects this.) */
2234
2235 #define REG_ALLOC_ORDER \
2236 { /* Accumulator registers. When GPRs and accumulators have equal \
2237 cost, we generally prefer to use accumulators. For example, \
2238 a division of multiplication result is better allocated to LO, \
2239 so that we put the MFLO at the point of use instead of at the \
2240 point of definition. It's also needed if we're to take advantage \
2241 of the extra accumulators available with -mdspr2. In some cases, \
2242 it can also help to reduce register pressure. */ \
2243 64, 65,176,177,178,179,180,181, \
2244 /* Call-clobbered GPRs. */ \
2245 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2246 24, 25, 31, \
2247 /* The global pointer. This is call-clobbered for o32 and o64 \
2248 abicalls, call-saved for n32 and n64 abicalls, and a program \
2249 invariant otherwise. Putting it between the call-clobbered \
2250 and call-saved registers should cope with all eventualities. */ \
2251 28, \
2252 /* Call-saved GPRs. */ \
2253 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2254 /* GPRs that can never be exposed to the register allocator. */ \
2255 0, 26, 27, 29, \
2256 /* Call-clobbered FPRs. */ \
2257 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2258 48, 49, 50, 51, \
2259 /* FPRs that are usually call-saved. The odd ones are actually \
2260 call-clobbered for n32, but listing them ahead of the even \
2261 registers might encourage the register allocator to fragment \
2262 the available FPR pairs. We need paired FPRs to store long \
2263 doubles, so it isn't clear that using a different order \
2264 for n32 would be a win. */ \
2265 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2266 /* None of the remaining classes have defined call-saved \
2267 registers. */ \
2268 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2269 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2270 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2271 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2272 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2273 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2274 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2275 182,183,184,185,186,187 \
2276 }
2277
2278 /* True if VALUE is an unsigned 6-bit number. */
2279
2280 #define UIMM6_OPERAND(VALUE) \
2281 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2282
2283 /* True if VALUE is a signed 10-bit number. */
2284
2285 #define IMM10_OPERAND(VALUE) \
2286 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2287
2288 /* True if VALUE is a signed 16-bit number. */
2289
2290 #define SMALL_OPERAND(VALUE) \
2291 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2292
2293 /* True if VALUE is an unsigned 16-bit number. */
2294
2295 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2296 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2297
2298 /* True if VALUE can be loaded into a register using LUI. */
2299
2300 #define LUI_OPERAND(VALUE) \
2301 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2302 || ((unsigned HOST_WIDE_INT) (VALUE) | 0x7fff0000) + 0x10000 == 0)
2303
2304 /* Return a value X with the low 16 bits clear, and such that
2305 VALUE - X is a signed 16-bit value. */
2306
2307 #define CONST_HIGH_PART(VALUE) \
2308 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2309
2310 #define CONST_LOW_PART(VALUE) \
2311 ((VALUE) - CONST_HIGH_PART (VALUE))
2312
2313 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2314 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2315 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2316 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2317 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2318
2319 /* The HI and LO registers can only be reloaded via the general
2320 registers. Condition code registers can only be loaded to the
2321 general registers, and from the floating point registers. */
2322
2323 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2324 mips_secondary_reload_class (CLASS, MODE, X, true)
2325 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2326 mips_secondary_reload_class (CLASS, MODE, X, false)
2327
2328 /* Return the maximum number of consecutive registers
2329 needed to represent mode MODE in a register of class CLASS. */
2330
2331 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2332
2333 /* Stack layout; function entry, exit and calling. */
2334
2335 #define STACK_GROWS_DOWNWARD 1
2336
2337 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
2338 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
2339
2340 /* Size of the area allocated in the frame to save the GP. */
2341
2342 #define MIPS_GP_SAVE_AREA_SIZE \
2343 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2344
2345 #define RETURN_ADDR_RTX mips_return_addr
2346
2347 /* Mask off the MIPS16 ISA bit in unwind addresses.
2348
2349 The reason for this is a little subtle. When unwinding a call,
2350 we are given the call's return address, which on most targets
2351 is the address of the following instruction. However, what we
2352 actually want to find is the EH region for the call itself.
2353 The target-independent unwind code therefore searches for "RA - 1".
2354
2355 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2356 RA - 1 is therefore the real (even-valued) start of the return
2357 instruction. EH region labels are usually odd-valued MIPS16 symbols
2358 too, so a search for an even address within a MIPS16 region would
2359 usually work.
2360
2361 However, there is an exception. If the end of an EH region is also
2362 the end of a function, the end label is allowed to be even. This is
2363 necessary because a following non-MIPS16 function may also need EH
2364 information for its first instruction.
2365
2366 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2367 non-ISA-encoded address. This probably isn't ideal, but it is
2368 the traditional (legacy) behavior. It is therefore only safe
2369 to search MIPS EH regions for an _odd-valued_ address.
2370
2371 Masking off the ISA bit means that the target-independent code
2372 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2373 #define MASK_RETURN_ADDR GEN_INT (-2)
2374
2375
2376 /* Similarly, don't use the least-significant bit to tell pointers to
2377 code from vtable index. */
2378
2379 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2380
2381 /* The eliminations to $17 are only used for mips16 code. See the
2382 definition of HARD_FRAME_POINTER_REGNUM. */
2383
2384 #define ELIMINABLE_REGS \
2385 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2386 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2387 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2388 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2389 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2390 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2391
2392 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2393 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2394
2395 /* Allocate stack space for arguments at the beginning of each function. */
2396 #define ACCUMULATE_OUTGOING_ARGS 1
2397
2398 /* The argument pointer always points to the first argument. */
2399 #define FIRST_PARM_OFFSET(FNDECL) 0
2400
2401 /* o32 and o64 reserve stack space for all argument registers. */
2402 #define REG_PARM_STACK_SPACE(FNDECL) \
2403 (TARGET_OLDABI \
2404 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2405 : 0)
2406
2407 /* Define this if it is the responsibility of the caller to
2408 allocate the area reserved for arguments passed in registers.
2409 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2410 of this macro is to determine whether the space is included in
2411 `crtl->outgoing_args_size'. */
2412 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2413
2414 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2415
2416 /* Symbolic macros for the registers used to return integer and floating
2417 point values. */
2418
2419 #define GP_RETURN (GP_REG_FIRST + 2)
2420 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2421
2422 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2423
2424 /* Symbolic macros for the first/last argument registers. */
2425
2426 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2427 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2428 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2429 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2430
2431 /* True if MODE is vector and supported in a MSA vector register. */
2432 #define MSA_SUPPORTED_MODE_P(MODE) \
2433 (ISA_HAS_MSA \
2434 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2435 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2436 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2437
2438 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2439 are used for returning complex double values in soft-float code, so $6 is the
2440 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2441 $gp itself as the temporary. */
2442 #define POST_CALL_TMP_REG \
2443 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2444
2445 /* 1 if N is a possible register number for function argument passing.
2446 We have no FP argument registers when soft-float. Special handling
2447 is required for O32 where only even numbered registers are used for
2448 O32-FPXX and O32-FP64. */
2449
2450 #define FUNCTION_ARG_REGNO_P(N) \
2451 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2452 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2453 && (mips_abi != ABI_32 \
2454 || TARGET_FLOAT32 \
2455 || ((N) % 2 == 0)))) \
2456 && !fixed_regs[N])
2457
2458 /* This structure has to cope with two different argument allocation
2459 schemes. Most MIPS ABIs view the arguments as a structure, of which
2460 the first N words go in registers and the rest go on the stack. If I
2461 < N, the Ith word might go in Ith integer argument register or in a
2462 floating-point register. For these ABIs, we only need to remember
2463 the offset of the current argument into the structure.
2464
2465 The EABI instead allocates the integer and floating-point arguments
2466 separately. The first N words of FP arguments go in FP registers,
2467 the rest go on the stack. Likewise, the first N words of the other
2468 arguments go in integer registers, and the rest go on the stack. We
2469 need to maintain three counts: the number of integer registers used,
2470 the number of floating-point registers used, and the number of words
2471 passed on the stack.
2472
2473 We could keep separate information for the two ABIs (a word count for
2474 the standard ABIs, and three separate counts for the EABI). But it
2475 seems simpler to view the standard ABIs as forms of EABI that do not
2476 allocate floating-point registers.
2477
2478 So for the standard ABIs, the first N words are allocated to integer
2479 registers, and mips_function_arg decides on an argument-by-argument
2480 basis whether that argument should really go in an integer register,
2481 or in a floating-point one. */
2482
2483 typedef struct mips_args {
2484 /* Always true for varargs functions. Otherwise true if at least
2485 one argument has been passed in an integer register. */
2486 int gp_reg_found;
2487
2488 /* The number of arguments seen so far. */
2489 unsigned int arg_number;
2490
2491 /* The number of integer registers used so far. For all ABIs except
2492 EABI, this is the number of words that have been added to the
2493 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2494 unsigned int num_gprs;
2495
2496 /* For EABI, the number of floating-point registers used so far. */
2497 unsigned int num_fprs;
2498
2499 /* The number of words passed on the stack. */
2500 unsigned int stack_words;
2501
2502 /* On the mips16, we need to keep track of which floating point
2503 arguments were passed in general registers, but would have been
2504 passed in the FP regs if this were a 32-bit function, so that we
2505 can move them to the FP regs if we wind up calling a 32-bit
2506 function. We record this information in fp_code, encoded in base
2507 four. A zero digit means no floating point argument, a one digit
2508 means an SFmode argument, and a two digit means a DFmode argument,
2509 and a three digit is not used. The low order digit is the first
2510 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2511 an SFmode argument. ??? A more sophisticated approach will be
2512 needed if MIPS_ABI != ABI_32. */
2513 int fp_code;
2514
2515 /* True if the function has a prototype. */
2516 int prototype;
2517 } CUMULATIVE_ARGS;
2518
2519 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2520 for a call to a function whose data type is FNTYPE.
2521 For a library call, FNTYPE is 0. */
2522
2523 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2524 mips_init_cumulative_args (&CUM, FNTYPE)
2525
2526 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2527 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2528
2529 /* True if using EABI and varargs can be passed in floating-point
2530 registers. Under these conditions, we need a more complex form
2531 of va_list, which tracks GPR, FPR and stack arguments separately. */
2532 #define EABI_FLOAT_VARARGS_P \
2533 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2534
2535
2536 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2537
2538 /* Treat LOC as a byte offset from the stack pointer and round it up
2539 to the next fully-aligned offset. */
2540 #define MIPS_STACK_ALIGN(LOC) \
2541 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2542
2543
2544 /* Output assembler code to FILE to increment profiler label # LABELNO
2545 for profiling a function entry. */
2546
2547 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2548
2549 /* The profiler preserves all interesting registers, including $31. */
2550 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2551
2552 /* No mips port has ever used the profiler counter word, so don't emit it
2553 or the label for it. */
2554
2555 #define NO_PROFILE_COUNTERS 1
2556
2557 /* Define this macro if the code for function profiling should come
2558 before the function prologue. Normally, the profiling code comes
2559 after. */
2560
2561 /* #define PROFILE_BEFORE_PROLOGUE */
2562
2563 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2564 the stack pointer does not matter. The value is tested only in
2565 functions that have frame pointers.
2566 No definition is equivalent to always zero. */
2567
2568 #define EXIT_IGNORE_STACK 1
2569
2570
2571 /* Trampolines are a block of code followed by two pointers. */
2572
2573 #define TRAMPOLINE_SIZE \
2574 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2575
2576 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2577 pointers from a single LUI base. */
2578
2579 #define TRAMPOLINE_ALIGNMENT 64
2580
2581 /* mips_trampoline_init calls this library function to flush
2582 program and data caches. */
2583
2584 #ifndef CACHE_FLUSH_FUNC
2585 #define CACHE_FLUSH_FUNC "_flush_cache"
2586 #endif
2587
2588 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2589 /* Flush both caches. We need to flush the data cache in case \
2590 the system has a write-back cache. */ \
2591 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2592 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2593 GEN_INT (3), TYPE_MODE (integer_type_node))
2594
2595
2596 /* Addressing modes, and classification of registers for them. */
2597
2598 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2599 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2600 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2601
2602 /* Maximum number of registers that can appear in a valid memory address. */
2603
2604 #define MAX_REGS_PER_ADDRESS 1
2605
2606 /* Check for constness inline but use mips_legitimate_address_p
2607 to check whether a constant really is an address. */
2608
2609 #define CONSTANT_ADDRESS_P(X) \
2610 (CONSTANT_P (X) && memory_address_p (SImode, X))
2611
2612 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2613 'the start of the function that this code is output in'. */
2614
2615 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2616 do { \
2617 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2618 asm_fprintf ((FILE), "%U%s", \
2619 XSTR (XEXP (DECL_RTL (current_function_decl), \
2620 0), 0)); \
2621 else \
2622 asm_fprintf ((FILE), "%U%s", (NAME)); \
2623 } while (0)
2624
2625 /* Flag to mark a function decl symbol that requires a long call. */
2626 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2627 #define SYMBOL_REF_LONG_CALL_P(X) \
2628 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2629
2630 /* This flag marks functions that cannot be lazily bound. */
2631 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2632 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2633 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2634
2635 /* True if we're generating a form of MIPS16 code in which jump tables
2636 are stored in the text section and encoded as 16-bit PC-relative
2637 offsets. This is only possible when general text loads are allowed,
2638 since the table access itself will be an "lh" instruction. If the
2639 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2640 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2641
2642 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2643
2644 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2645
2646 /* Only use short offsets if their range will not overflow. */
2647 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2648 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2649 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2650 : SImode)
2651
2652 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2653
2654 /* Define this as 1 if `char' should by default be signed; else as 0. */
2655 #ifndef DEFAULT_SIGNED_CHAR
2656 #define DEFAULT_SIGNED_CHAR 1
2657 #endif
2658
2659 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2660 we generally don't want to use them for copying arbitrary data.
2661 A single N-word move is usually the same cost as N single-word moves. */
2662 #define MOVE_MAX UNITS_PER_WORD
2663 /* We don't modify it for MSA as it is only used by the classic reload. */
2664 #define MAX_MOVE_MAX 8
2665
2666 /* Define this macro as a C expression which is nonzero if
2667 accessing less than a word of memory (i.e. a `char' or a
2668 `short') is no faster than accessing a word of memory, i.e., if
2669 such access require more than one instruction or if there is no
2670 difference in cost between byte and (aligned) word loads.
2671
2672 On RISC machines, it tends to generate better code to define
2673 this as 1, since it avoids making a QI or HI mode register.
2674
2675 But, generating word accesses for -mips16 is generally bad as shifts
2676 (often extended) would be needed for byte accesses. */
2677 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2678
2679 /* Standard MIPS integer shifts truncate the shift amount to the
2680 width of the shifted operand. However, Loongson MMI shifts
2681 do not truncate the shift amount at all. */
2682 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI)
2683
2684
2685 /* Specify the machine mode that pointers have.
2686 After generation of rtl, the compiler makes no further distinction
2687 between pointers and any other objects of this machine mode. */
2688
2689 #ifndef Pmode
2690 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2691 #endif
2692
2693 /* Give call MEMs SImode since it is the "most permissive" mode
2694 for both 32-bit and 64-bit targets. */
2695
2696 #define FUNCTION_MODE SImode
2697
2698
2699 /* We allocate $fcc registers by hand and can't cope with moves of
2700 CCmode registers to and from pseudos (or memory). */
2701 #define AVOID_CCMODE_COPIES
2702
2703 /* A C expression for the cost of a branch instruction. A value of
2704 1 is the default; other values are interpreted relative to that. */
2705
2706 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2707 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2708
2709 /* The MIPS port has several functions that return an instruction count.
2710 Multiplying the count by this value gives the number of bytes that
2711 the instructions occupy. */
2712 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2713
2714 /* The length of a NOP in bytes. */
2715 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2716
2717 /* If defined, modifies the length assigned to instruction INSN as a
2718 function of the context in which it is used. LENGTH is an lvalue
2719 that contains the initially computed length of the insn and should
2720 be updated with the correct length of the insn. */
2721 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2722 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2723
2724 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2725 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2726 its operands. */
2727 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2728 "%*" OPCODE "%?\t" OPERANDS "%/"
2729
2730 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2731 "%*" OPCODE "%:\t" OPERANDS
2732
2733 /* Return an asm string that forces INSN to be treated as an absolute
2734 J or JAL instruction instead of an assembler macro. */
2735 #define MIPS_ABSOLUTE_JUMP(INSN) \
2736 (TARGET_ABICALLS_PIC2 \
2737 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2738 : INSN)
2739
2740
2741 /* Control the assembler format that we output. */
2742
2743 /* Output to assembler file text saying following lines
2744 may contain character constants, extra white space, comments, etc. */
2745
2746 #ifndef ASM_APP_ON
2747 #define ASM_APP_ON " #APP\n"
2748 #endif
2749
2750 /* Output to assembler file text saying following lines
2751 no longer contain unusual constructs. */
2752
2753 #ifndef ASM_APP_OFF
2754 #define ASM_APP_OFF " #NO_APP\n"
2755 #endif
2756
2757 #define REGISTER_NAMES \
2758 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2759 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2760 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2761 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2762 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2763 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2764 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2765 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2766 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2767 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2768 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2769 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2770 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2771 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2772 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2773 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2774 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2775 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2776 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2777 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2778 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2779 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2780 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2781 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2782
2783 /* List the "software" names for each register. Also list the numerical
2784 names for $fp and $sp. */
2785
2786 #define ADDITIONAL_REGISTER_NAMES \
2787 { \
2788 { "$29", 29 + GP_REG_FIRST }, \
2789 { "$30", 30 + GP_REG_FIRST }, \
2790 { "at", 1 + GP_REG_FIRST }, \
2791 { "v0", 2 + GP_REG_FIRST }, \
2792 { "v1", 3 + GP_REG_FIRST }, \
2793 { "a0", 4 + GP_REG_FIRST }, \
2794 { "a1", 5 + GP_REG_FIRST }, \
2795 { "a2", 6 + GP_REG_FIRST }, \
2796 { "a3", 7 + GP_REG_FIRST }, \
2797 { "t0", 8 + GP_REG_FIRST }, \
2798 { "t1", 9 + GP_REG_FIRST }, \
2799 { "t2", 10 + GP_REG_FIRST }, \
2800 { "t3", 11 + GP_REG_FIRST }, \
2801 { "t4", 12 + GP_REG_FIRST }, \
2802 { "t5", 13 + GP_REG_FIRST }, \
2803 { "t6", 14 + GP_REG_FIRST }, \
2804 { "t7", 15 + GP_REG_FIRST }, \
2805 { "s0", 16 + GP_REG_FIRST }, \
2806 { "s1", 17 + GP_REG_FIRST }, \
2807 { "s2", 18 + GP_REG_FIRST }, \
2808 { "s3", 19 + GP_REG_FIRST }, \
2809 { "s4", 20 + GP_REG_FIRST }, \
2810 { "s5", 21 + GP_REG_FIRST }, \
2811 { "s6", 22 + GP_REG_FIRST }, \
2812 { "s7", 23 + GP_REG_FIRST }, \
2813 { "t8", 24 + GP_REG_FIRST }, \
2814 { "t9", 25 + GP_REG_FIRST }, \
2815 { "k0", 26 + GP_REG_FIRST }, \
2816 { "k1", 27 + GP_REG_FIRST }, \
2817 { "gp", 28 + GP_REG_FIRST }, \
2818 { "sp", 29 + GP_REG_FIRST }, \
2819 { "fp", 30 + GP_REG_FIRST }, \
2820 { "ra", 31 + GP_REG_FIRST }, \
2821 { "$w0", 0 + FP_REG_FIRST }, \
2822 { "$w1", 1 + FP_REG_FIRST }, \
2823 { "$w2", 2 + FP_REG_FIRST }, \
2824 { "$w3", 3 + FP_REG_FIRST }, \
2825 { "$w4", 4 + FP_REG_FIRST }, \
2826 { "$w5", 5 + FP_REG_FIRST }, \
2827 { "$w6", 6 + FP_REG_FIRST }, \
2828 { "$w7", 7 + FP_REG_FIRST }, \
2829 { "$w8", 8 + FP_REG_FIRST }, \
2830 { "$w9", 9 + FP_REG_FIRST }, \
2831 { "$w10", 10 + FP_REG_FIRST }, \
2832 { "$w11", 11 + FP_REG_FIRST }, \
2833 { "$w12", 12 + FP_REG_FIRST }, \
2834 { "$w13", 13 + FP_REG_FIRST }, \
2835 { "$w14", 14 + FP_REG_FIRST }, \
2836 { "$w15", 15 + FP_REG_FIRST }, \
2837 { "$w16", 16 + FP_REG_FIRST }, \
2838 { "$w17", 17 + FP_REG_FIRST }, \
2839 { "$w18", 18 + FP_REG_FIRST }, \
2840 { "$w19", 19 + FP_REG_FIRST }, \
2841 { "$w20", 20 + FP_REG_FIRST }, \
2842 { "$w21", 21 + FP_REG_FIRST }, \
2843 { "$w22", 22 + FP_REG_FIRST }, \
2844 { "$w23", 23 + FP_REG_FIRST }, \
2845 { "$w24", 24 + FP_REG_FIRST }, \
2846 { "$w25", 25 + FP_REG_FIRST }, \
2847 { "$w26", 26 + FP_REG_FIRST }, \
2848 { "$w27", 27 + FP_REG_FIRST }, \
2849 { "$w28", 28 + FP_REG_FIRST }, \
2850 { "$w29", 29 + FP_REG_FIRST }, \
2851 { "$w30", 30 + FP_REG_FIRST }, \
2852 { "$w31", 31 + FP_REG_FIRST } \
2853 }
2854
2855 #define DBR_OUTPUT_SEQEND(STREAM) \
2856 do \
2857 { \
2858 /* Undo the effect of '%*'. */ \
2859 mips_pop_asm_switch (&mips_nomacro); \
2860 mips_pop_asm_switch (&mips_noreorder); \
2861 /* Emit a blank line after the delay slot for emphasis. */ \
2862 fputs ("\n", STREAM); \
2863 } \
2864 while (0)
2865
2866 /* The MIPS implementation uses some labels for its own purpose. The
2867 following lists what labels are created, and are all formed by the
2868 pattern $L[a-z].*. The machine independent portion of GCC creates
2869 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2870
2871 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2872 $Lb[0-9]+ Begin blocks for MIPS debug support
2873 $Lc[0-9]+ Label for use in s<xx> operation.
2874 $Le[0-9]+ End blocks for MIPS debug support */
2875
2876 #undef ASM_DECLARE_OBJECT_NAME
2877 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2878 mips_declare_object (STREAM, NAME, "", ":\n")
2879
2880 /* Globalizing directive for a label. */
2881 #define GLOBAL_ASM_OP "\t.globl\t"
2882
2883 /* This says how to define a global common symbol. */
2884
2885 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2886
2887 /* This says how to define a local common symbol (i.e., not visible to
2888 linker). */
2889
2890 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2891 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2892 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2893 #endif
2894
2895 /* This says how to output an external. It would be possible not to
2896 output anything and let undefined symbol become external. However
2897 the assembler uses length information on externals to allocate in
2898 data/sdata bss/sbss, thereby saving exec time. */
2899
2900 #undef ASM_OUTPUT_EXTERNAL
2901 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2902 mips_output_external(STREAM,DECL,NAME)
2903
2904 /* This is how to declare a function name. The actual work of
2905 emitting the label is moved to function_prologue, so that we can
2906 get the line number correctly emitted before the .ent directive,
2907 and after any .file directives. Define as empty so that the function
2908 is not declared before the .ent directive elsewhere. */
2909
2910 #undef ASM_DECLARE_FUNCTION_NAME
2911 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2912
2913 /* This is how to store into the string LABEL
2914 the symbol_ref name of an internal numbered label where
2915 PREFIX is the class of label and NUM is the number within the class.
2916 This is suitable for output with `assemble_name'. */
2917
2918 #undef ASM_GENERATE_INTERNAL_LABEL
2919 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2920 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2921
2922 /* Print debug labels as "foo = ." rather than "foo:" because they should
2923 represent a byte pointer rather than an ISA-encoded address. This is
2924 particularly important for code like:
2925
2926 $LFBxxx = .
2927 .cfi_startproc
2928 ...
2929 .section .gcc_except_table,...
2930 ...
2931 .uleb128 foo-$LFBxxx
2932
2933 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2934 likewise a byte pointer rather than an ISA-encoded address.
2935
2936 At the time of writing, this hook is not used for the function end
2937 label:
2938
2939 $LFExxx:
2940 .end foo
2941
2942 But this doesn't matter, because GAS doesn't treat a pre-.end label
2943 as a MIPS16 one anyway. */
2944
2945 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2946 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2947
2948 /* This is how to output an element of a case-vector that is absolute. */
2949
2950 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2951 fprintf (STREAM, "\t%s\t%sL%d\n", \
2952 ptr_mode == DImode ? ".dword" : ".word", \
2953 LOCAL_LABEL_PREFIX, \
2954 VALUE)
2955
2956 /* This is how to output an element of a case-vector. We can make the
2957 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2958 is supported. */
2959
2960 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2961 do { \
2962 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2963 { \
2964 if (GET_MODE (BODY) == HImode) \
2965 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2966 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2967 else \
2968 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2969 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2970 } \
2971 else if (TARGET_GPWORD) \
2972 fprintf (STREAM, "\t%s\t%sL%d\n", \
2973 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2974 LOCAL_LABEL_PREFIX, VALUE); \
2975 else if (TARGET_RTP_PIC) \
2976 { \
2977 /* Make the entry relative to the start of the function. */ \
2978 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2979 fprintf (STREAM, "\t%s\t%sL%d-", \
2980 Pmode == DImode ? ".dword" : ".word", \
2981 LOCAL_LABEL_PREFIX, VALUE); \
2982 assemble_name (STREAM, XSTR (fnsym, 0)); \
2983 fprintf (STREAM, "\n"); \
2984 } \
2985 else \
2986 fprintf (STREAM, "\t%s\t%sL%d\n", \
2987 ptr_mode == DImode ? ".dword" : ".word", \
2988 LOCAL_LABEL_PREFIX, VALUE); \
2989 } while (0)
2990
2991 /* Mark inline jump tables as data for the purpose of disassembly. For
2992 simplicity embed the jump table's label number in the local symbol
2993 produced so that multiple jump tables within a single function end
2994 up marked with unique symbols. Retain the alignment setting from
2995 `elfos.h' as we are replacing the definition from there. */
2996
2997 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2998 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
2999 do \
3000 { \
3001 ASM_OUTPUT_ALIGN ((STREAM), 2); \
3002 if (JUMP_TABLES_IN_TEXT_SECTION) \
3003 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
3004 } \
3005 while (0)
3006
3007 /* Reset text marking to code after an inline jump table. Like with
3008 the beginning of a jump table use the label number to keep symbols
3009 unique. */
3010
3011 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
3012 do \
3013 if (JUMP_TABLES_IN_TEXT_SECTION) \
3014 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
3015 while (0)
3016
3017 /* This is how to output an assembler line
3018 that says to advance the location counter
3019 to a multiple of 2**LOG bytes. */
3020
3021 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3022 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3023
3024 /* This is how to output an assembler line to advance the location
3025 counter by SIZE bytes. */
3026
3027 #undef ASM_OUTPUT_SKIP
3028 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3029 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3030
3031 /* This is how to output a string. */
3032 #undef ASM_OUTPUT_ASCII
3033 #define ASM_OUTPUT_ASCII mips_output_ascii
3034
3035
3036 /* Default to -G 8 */
3037 #ifndef MIPS_DEFAULT_GVALUE
3038 #define MIPS_DEFAULT_GVALUE 8
3039 #endif
3040
3041 /* Define the strings to put out for each section in the object file. */
3042 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3043 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3044
3045 #undef READONLY_DATA_SECTION_ASM_OP
3046 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3047
3048 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3049 do \
3050 { \
3051 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3052 TARGET_64BIT ? "daddiu" : "addiu", \
3053 reg_names[STACK_POINTER_REGNUM], \
3054 reg_names[STACK_POINTER_REGNUM], \
3055 TARGET_64BIT ? "sd" : "sw", \
3056 reg_names[REGNO], \
3057 reg_names[STACK_POINTER_REGNUM]); \
3058 } \
3059 while (0)
3060
3061 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3062 do \
3063 { \
3064 mips_push_asm_switch (&mips_noreorder); \
3065 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3066 TARGET_64BIT ? "ld" : "lw", \
3067 reg_names[REGNO], \
3068 reg_names[STACK_POINTER_REGNUM], \
3069 TARGET_64BIT ? "daddu" : "addu", \
3070 reg_names[STACK_POINTER_REGNUM], \
3071 reg_names[STACK_POINTER_REGNUM]); \
3072 mips_pop_asm_switch (&mips_noreorder); \
3073 } \
3074 while (0)
3075
3076 /* How to start an assembler comment.
3077 The leading space is important (the mips native assembler requires it). */
3078 #ifndef ASM_COMMENT_START
3079 #define ASM_COMMENT_START " #"
3080 #endif
3081
3082 #undef SIZE_TYPE
3083 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3084
3085 #undef PTRDIFF_TYPE
3086 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3087
3088 /* The minimum alignment of any expanded block move. */
3089 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3090
3091 /* The maximum number of bytes that can be copied by one iteration of
3092 a cpymemsi loop; see mips_block_move_loop. */
3093 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3094 (UNITS_PER_WORD * 4)
3095
3096 /* The maximum number of bytes that can be copied by a straight-line
3097 implementation of cpymemsi; see mips_block_move_straight. We want
3098 to make sure that any loop-based implementation will iterate at
3099 least twice. */
3100 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3101 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3102
3103 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3104 values were determined experimentally by benchmarking with CSiBE.
3105 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3106 for o32 where we have to restore $gp afterwards as well as make an
3107 indirect call), but in practice, bumping this up higher for
3108 TARGET_ABICALLS doesn't make much difference to code size. */
3109
3110 #define MIPS_CALL_RATIO 8
3111
3112 /* Any loop-based implementation of cpymemsi will have at least
3113 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3114 moves, so allow individual copies of fewer elements.
3115
3116 When cpymemsi is not available, use a value approximating
3117 the length of a memcpy call sequence, so that move_by_pieces
3118 will generate inline code if it is shorter than a function call.
3119 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3120 we'll have to generate a load/store pair for each, halve the
3121 value of MIPS_CALL_RATIO to take that into account. */
3122
3123 #define MOVE_RATIO(speed) \
3124 (HAVE_cpymemsi \
3125 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3126 : MIPS_CALL_RATIO / 2)
3127
3128 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3129 of the length of a memset call, but use the default otherwise. */
3130
3131 #define CLEAR_RATIO(speed)\
3132 ((speed) ? 15 : MIPS_CALL_RATIO)
3133
3134 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3135 optimizing for size adjust the ratio to account for the overhead of
3136 loading the constant and replicating it across the word. */
3137
3138 #define SET_RATIO(speed) \
3139 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3140
3141 /* Since the bits of the _init and _fini function is spread across
3142 many object files, each potentially with its own GP, we must assume
3143 we need to load our GP. We don't preserve $gp or $ra, since each
3144 init/fini chunk is supposed to initialize $gp, and crti/crtn
3145 already take care of preserving $ra and, when appropriate, $gp. */
3146 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3147 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3148 asm (SECTION_OP "\n\
3149 .set push\n\
3150 .set nomips16\n\
3151 .set noreorder\n\
3152 bal 1f\n\
3153 nop\n\
3154 1: .cpload $31\n\
3155 .set reorder\n\
3156 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3157 jalr $25\n\
3158 .set pop\n\
3159 " TEXT_SECTION_ASM_OP);
3160 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3161 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3162 asm (SECTION_OP "\n\
3163 .set push\n\
3164 .set nomips16\n\
3165 .set noreorder\n\
3166 bal 1f\n\
3167 nop\n\
3168 1: .set reorder\n\
3169 .cpsetup $31, $2, 1b\n\
3170 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3171 jalr $25\n\
3172 .set pop\n\
3173 " TEXT_SECTION_ASM_OP);
3174 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3175 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3176 asm (SECTION_OP "\n\
3177 .set push\n\
3178 .set nomips16\n\
3179 .set noreorder\n\
3180 bal 1f\n\
3181 nop\n\
3182 1: .set reorder\n\
3183 .cpsetup $31, $2, 1b\n\
3184 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3185 jalr $25\n\
3186 .set pop\n\
3187 " TEXT_SECTION_ASM_OP);
3188 #endif
3189
3190 #ifndef HAVE_AS_TLS
3191 #define HAVE_AS_TLS 0
3192 #endif
3193
3194 #ifndef HAVE_AS_NAN
3195 #define HAVE_AS_NAN 0
3196 #endif
3197
3198 #ifndef USED_FOR_TARGET
3199 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3200 struct mips_asm_switch {
3201 /* The FOO in the description above. */
3202 const char *name;
3203
3204 /* The current block nesting level, or 0 if we aren't in a block. */
3205 int nesting_level;
3206 };
3207
3208 extern const enum reg_class mips_regno_to_class[];
3209 extern const char *current_function_file; /* filename current function is in */
3210 extern int num_source_filenames; /* current .file # */
3211 extern struct mips_asm_switch mips_noreorder;
3212 extern struct mips_asm_switch mips_nomacro;
3213 extern struct mips_asm_switch mips_noat;
3214 extern int mips_dwarf_regno[];
3215 extern bool mips_split_p[];
3216 extern bool mips_split_hi_p[];
3217 extern bool mips_use_pcrel_pool_p[];
3218 extern const char *mips_lo_relocs[];
3219 extern const char *mips_hi_relocs[];
3220 extern enum processor mips_arch; /* which cpu to codegen for */
3221 extern enum processor mips_tune; /* which cpu to schedule for */
3222 extern int mips_isa; /* architectural level */
3223 extern int mips_isa_rev;
3224 extern const struct mips_cpu_info *mips_arch_info;
3225 extern const struct mips_cpu_info *mips_tune_info;
3226 extern unsigned int mips_base_compression_flags;
3227 extern GTY(()) struct target_globals *mips16_globals;
3228 extern GTY(()) struct target_globals *micromips_globals;
3229
3230 /* Information about a function's frame layout. */
3231 struct GTY(()) mips_frame_info {
3232 /* The size of the frame in bytes. */
3233 HOST_WIDE_INT total_size;
3234
3235 /* The number of bytes allocated to variables. */
3236 HOST_WIDE_INT var_size;
3237
3238 /* The number of bytes allocated to outgoing function arguments. */
3239 HOST_WIDE_INT args_size;
3240
3241 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3242 is no such slot. */
3243 HOST_WIDE_INT cprestore_size;
3244
3245 /* Bit X is set if the function saves or restores GPR X. */
3246 unsigned int mask;
3247
3248 /* Likewise FPR X. */
3249 unsigned int fmask;
3250
3251 /* Likewise doubleword accumulator X ($acX). */
3252 unsigned int acc_mask;
3253
3254 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3255 registers saved. */
3256 unsigned int num_gp;
3257 unsigned int num_fp;
3258 unsigned int num_acc;
3259 unsigned int num_cop0_regs;
3260
3261 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3262 save slots from the top of the frame, or zero if no such slots are
3263 needed. */
3264 HOST_WIDE_INT gp_save_offset;
3265 HOST_WIDE_INT fp_save_offset;
3266 HOST_WIDE_INT acc_save_offset;
3267 HOST_WIDE_INT cop0_save_offset;
3268
3269 /* Likewise, but giving offsets from the bottom of the frame. */
3270 HOST_WIDE_INT gp_sp_offset;
3271 HOST_WIDE_INT fp_sp_offset;
3272 HOST_WIDE_INT acc_sp_offset;
3273 HOST_WIDE_INT cop0_sp_offset;
3274
3275 /* Similar, but the value passed to _mcount. */
3276 HOST_WIDE_INT ra_fp_offset;
3277
3278 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3279 HOST_WIDE_INT arg_pointer_offset;
3280
3281 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3282 HOST_WIDE_INT hard_frame_pointer_offset;
3283 };
3284
3285 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3286 enum mips_int_mask
3287 {
3288 INT_MASK_EIC = -1,
3289 INT_MASK_SW0 = 0,
3290 INT_MASK_SW1 = 1,
3291 INT_MASK_HW0 = 2,
3292 INT_MASK_HW1 = 3,
3293 INT_MASK_HW2 = 4,
3294 INT_MASK_HW3 = 5,
3295 INT_MASK_HW4 = 6,
3296 INT_MASK_HW5 = 7
3297 };
3298
3299 /* Enumeration to mark the existence of the shadow register set.
3300 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3301 pointer. */
3302 enum mips_shadow_set
3303 {
3304 SHADOW_SET_NO,
3305 SHADOW_SET_YES,
3306 SHADOW_SET_INTSTACK
3307 };
3308
3309 struct GTY(()) machine_function {
3310 /* The next floating-point condition-code register to allocate
3311 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3312 unsigned int next_fcc;
3313
3314 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3315 rtx mips16_gp_pseudo_rtx;
3316
3317 /* The number of extra stack bytes taken up by register varargs.
3318 This area is allocated by the callee at the very top of the frame. */
3319 int varargs_size;
3320
3321 /* The current frame information, calculated by mips_compute_frame_info. */
3322 struct mips_frame_info frame;
3323
3324 /* The register to use as the function's global pointer, or INVALID_REGNUM
3325 if the function doesn't need one. */
3326 unsigned int global_pointer;
3327
3328 /* How many instructions it takes to load a label into $AT, or 0 if
3329 this property hasn't yet been calculated. */
3330 unsigned int load_label_num_insns;
3331
3332 /* True if mips_adjust_insn_length should ignore an instruction's
3333 hazard attribute. */
3334 bool ignore_hazard_length_p;
3335
3336 /* True if the whole function is suitable for .set noreorder and
3337 .set nomacro. */
3338 bool all_noreorder_p;
3339
3340 /* True if the function has "inflexible" and "flexible" references
3341 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3342 and mips_cfun_has_flexible_gp_ref_p for details. */
3343 bool has_inflexible_gp_insn_p;
3344 bool has_flexible_gp_insn_p;
3345
3346 /* True if the function's prologue must load the global pointer
3347 value into pic_offset_table_rtx and store the same value in
3348 the function's cprestore slot (if any). Even if this value
3349 is currently false, we may decide to set it to true later;
3350 see mips_must_initialize_gp_p () for details. */
3351 bool must_initialize_gp_p;
3352
3353 /* True if the current function must restore $gp after any potential
3354 clobber. This value is only meaningful during the first post-epilogue
3355 split_insns pass; see mips_must_initialize_gp_p () for details. */
3356 bool must_restore_gp_when_clobbered_p;
3357
3358 /* True if this is an interrupt handler. */
3359 bool interrupt_handler_p;
3360
3361 /* Records the way in which interrupts should be masked. Only used if
3362 interrupts are not kept masked. */
3363 enum mips_int_mask int_mask;
3364
3365 /* Records if this is an interrupt handler that uses shadow registers. */
3366 enum mips_shadow_set use_shadow_register_set;
3367
3368 /* True if this is an interrupt handler that should keep interrupts
3369 masked. */
3370 bool keep_interrupts_masked_p;
3371
3372 /* True if this is an interrupt handler that should use DERET
3373 instead of ERET. */
3374 bool use_debug_exception_return_p;
3375
3376 /* True if at least one of the formal parameters to a function must be
3377 written to the frame header (probably so its address can be taken). */
3378 bool does_not_use_frame_header;
3379
3380 /* True if none of the functions that are called by this function need
3381 stack space allocated for their arguments. */
3382 bool optimize_call_stack;
3383
3384 /* True if one of the functions calling this function may not allocate
3385 a frame header. */
3386 bool callers_may_not_allocate_frame;
3387
3388 /* True if GCC stored callee saved registers in the frame header. */
3389 bool use_frame_header_for_callee_saved_regs;
3390
3391 /* True if the function should generate hazard barrier return. */
3392 bool use_hazard_barrier_return_p;
3393 };
3394 #endif
3395
3396 /* Enable querying of DFA units. */
3397 #define CPU_UNITS_QUERY 1
3398
3399 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3400 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3401
3402 /* As on most targets, we want the .eh_frame section to be read-only where
3403 possible. And as on most targets, this means two things:
3404
3405 (a) Non-locally-binding pointers must have an indirect encoding,
3406 so that the addresses in the .eh_frame section itself become
3407 locally-binding.
3408
3409 (b) A shared library's .eh_frame section must encode locally-binding
3410 pointers in a relative (relocation-free) form.
3411
3412 However, MIPS has traditionally not allowed directives like:
3413
3414 .long x-.
3415
3416 in cases where "x" is in a different section, or is not defined in the
3417 same assembly file. We are therefore unable to emit the PC-relative
3418 form required by (b) at assembly time.
3419
3420 Fortunately, the linker is able to convert absolute addresses into
3421 PC-relative addresses on our behalf. Unfortunately, only certain
3422 versions of the linker know how to do this for indirect pointers,
3423 and for personality data. We must fall back on using writable
3424 .eh_frame sections for shared libraries if the linker does not
3425 support this feature. */
3426 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3427 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3428
3429 /* For switching between MIPS16 and non-MIPS16 modes. */
3430 #define SWITCHABLE_TARGET 1
3431
3432 /* Several named MIPS patterns depend on Pmode. These patterns have the
3433 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3434 Add the appropriate suffix to generator function NAME and invoke it
3435 with arguments ARGS. */
3436 #define PMODE_INSN(NAME, ARGS) \
3437 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3438
3439 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3440 need to change these from /lib and /usr/lib. */
3441 #ifndef ENABLE_MULTIARCH
3442 #if MIPS_ABI_DEFAULT == ABI_N32
3443 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3444 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3445 #elif MIPS_ABI_DEFAULT == ABI_64
3446 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3447 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3448 #endif
3449 #endif
3450
3451 /* Load store bonding is not supported by micromips and fix_24k. The
3452 performance can be degraded for those targets. Hence, do not bond for
3453 micromips or fix_24k. */
3454 #define ENABLE_LD_ST_PAIRS \
3455 (TARGET_LOAD_STORE_PAIRS \
3456 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
3457 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
3458
3459 #define NEED_INDICATE_EXEC_STACK 0