1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993-2023 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef GCC_MCORE_H
22 #define GCC_MCORE_H
23
24 /* RBE: need to move these elsewhere. */
25 #undef LIKE_PPC_ABI
26 #define MCORE_STRUCT_ARGS
27 /* RBE: end of "move elsewhere". */
28
29 /* Run-time Target Specification. */
30 #define TARGET_MCORE
31
32 /* Get tree.cc to declare a target-specific specialization of
33 merge_decl_attributes. */
34 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1
35
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do \
38 { \
39 builtin_define ("__mcore__"); \
40 builtin_define ("__MCORE__"); \
41 if (TARGET_LITTLE_END) \
42 builtin_define ("__MCORELE__"); \
43 else \
44 builtin_define ("__MCOREBE__"); \
45 if (TARGET_M340) \
46 builtin_define ("__M340__"); \
47 else \
48 builtin_define ("__M210__"); \
49 } \
50 while (0)
51
52 #undef CPP_SPEC
53 #define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}"
54
55 /* We don't have a -lg library, so don't put it in the list. */
56 #undef LIB_SPEC
57 #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
58
59 #undef ASM_SPEC
60 #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}"
61
62 #undef LINK_SPEC
63 #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X"
64
65 #define TARGET_DEFAULT \
66 (MASK_HARDLIT \
67 | MASK_DIV \
68 | MASK_RELAX_IMM \
69 | MASK_M340 \
70 | MASK_LITTLE_END)
71
72 #ifndef MULTILIB_DEFAULTS
73 #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" }
74 #endif
75
76 /* The ability to have 4 byte alignment is being suppressed for now.
77 If this ability is reenabled, you must disable the definition below
78 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
79 #undef TARGET_8ALIGN
80 #define TARGET_8ALIGN 1
81
82 extern char * mcore_current_function_name;
83
84 /* The MCore ABI says that bitfields are unsigned by default. */
85 #define CC1_SPEC "-funsigned-bitfields"
86
87 /* Target machine storage Layout. */
88
89 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
90 if (GET_MODE_CLASS (MODE) == MODE_INT \
91 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
92 { \
93 (MODE) = SImode; \
94 (UNSIGNEDP) = 1; \
95 }
96
97 /* Define this if most significant bit is lowest numbered
98 in instructions that operate on numbered bit-fields. */
99 #define BITS_BIG_ENDIAN 0
100
101 /* Define this if most significant byte of a word is the lowest numbered. */
102 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
103
104 /* Define this if most significant word of a multiword number is the lowest
105 numbered. */
106 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
107
108 #define MAX_BITS_PER_WORD 32
109
110 /* Width of a word, in units (bytes). */
111 #define UNITS_PER_WORD 4
112
113 /* A C expression for the size in bits of the type `long long' on the
114 target machine. If you don't define this, the default is two
115 words. */
116 #define LONG_LONG_TYPE_SIZE 64
117
118 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
119 #define PARM_BOUNDARY 32
120
121 /* Boundary (in *bits*) on which stack pointer should be aligned. */
122 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
123
124 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
125 #define STACK_UNITS_MAXSTEP 4096
126
127 /* Allocation boundary (in *bits*) for the code of a function. */
128 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
129
130 /* Alignment of field after `int : 0' in a structure. */
131 #define EMPTY_FIELD_BOUNDARY 32
132
133 /* No data type wants to be aligned rounder than this. */
134 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
135
136 /* The best alignment to use in cases where we have a choice. */
137 #define FASTEST_ALIGNMENT 32
138
139 /* Every structures size must be a multiple of 8 bits. */
140 #define STRUCTURE_SIZE_BOUNDARY 8
141
142 /* Look at the fundamental type that is used for a bit-field and use
143 that to impose alignment on the enclosing structure.
144 struct s {int a:8}; should have same alignment as "int", not "char". */
145 #define PCC_BITFIELD_TYPE_MATTERS 1
146
147 /* Largest integer machine mode for structures. If undefined, the default
148 is GET_MODE_SIZE(DImode). */
149 #define MAX_FIXED_MODE_SIZE 32
150
151 /* Make arrays of chars word-aligned for the same reasons. */
152 #define DATA_ALIGNMENT(TYPE, ALIGN) \
153 (TREE_CODE (TYPE) == ARRAY_TYPE \
154 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
155 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
156
157 /* Set this nonzero if move instructions will actually fail to work
158 when given unaligned data. */
159 #define STRICT_ALIGNMENT 1
160
161 /* Standard register usage. */
162
163 /* Register allocation for our first guess
164
165 r0 stack pointer
166 r1 scratch, target reg for xtrb?
167 r2-r7 arguments.
168 r8-r14 call saved
169 r15 link register
170 ap arg pointer (doesn't really exist, always eliminated)
171 c c bit
172 fp frame pointer (doesn't really exist, always eliminated)
173 x19 two control registers. */
174
175 /* Number of actual hardware registers.
176 The hardware registers are assigned numbers for the compiler
177 from 0 to just below FIRST_PSEUDO_REGISTER.
178 All registers that the compiler knows about must be given numbers,
179 even those that are not normally considered general registers.
180
181 MCore has 16 integer registers and 2 control registers + the arg
182 pointer. */
183
184 #define FIRST_PSEUDO_REGISTER 20
185
186 #define R1_REG 1 /* Where literals are forced. */
187 #define LK_REG 15 /* Overloaded on general register. */
188 #define AP_REG 16 /* Fake arg pointer register. */
189 /* RBE: mcore.md depends on CC_REG being set to 17. */
190 #define CC_REG 17 /* Can't name it C_REG. */
191 #define FP_REG 18 /* Fake frame pointer register. */
192
193 /* Specify the registers used for certain standard purposes.
194 The values of these macros are register numbers. */
195
196
197 #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */
198 #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */
199 #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */
200
201 /* The assembler's names for the registers. RFP need not always be used as
202 the Real framepointer; it can also be used as a normal general register.
203 Note that the name `fp' is horribly misleading since `fp' is in fact only
204 the argument-and-return-context pointer. */
205 #define REGISTER_NAMES \
206 { \
207 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
209 "apvirtual", "c", "fpvirtual", "x19" \
210 }
211
212 /* 1 for registers that have pervasive standard uses
213 and are not available for the register allocator. */
214 #define FIXED_REGISTERS \
215 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
216 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
217
218 /* 1 for registers not available across function calls.
219 These must include the FIXED_REGISTERS and also any
220 registers that can be used without being saved.
221 The latter must include the registers where values are returned
222 and the register where structure-value addresses are passed.
223 Aside from that, you can include as many other registers as you like. */
224
225 /* RBE: r15 {link register} not available across calls,
226 But we don't mark it that way here.... */
227 #define CALL_USED_REGISTERS \
228 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
229 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
230
231 /* The order in which register should be allocated. */
232 #define REG_ALLOC_ORDER \
233 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \
234 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
235
236 /* Definitions for register eliminations.
237
238 We have two registers that can be eliminated on the MCore. First, the
239 frame pointer register can often be eliminated in favor of the stack
240 pointer register. Secondly, the argument pointer register can always be
241 eliminated; it is replaced with either the stack or frame pointer. */
242
243 /* Base register for access to arguments of the function. */
244 #define ARG_POINTER_REGNUM 16
245
246 /* Register in which the static-chain is passed to a function. */
247 #define STATIC_CHAIN_REGNUM 1
248
249 /* This is an array of structures. Each structure initializes one pair
250 of eliminable registers. The "from" register number is given first,
251 followed by "to". Eliminations of the same "from" register are listed
252 in order of preference. */
253 #define ELIMINABLE_REGS \
254 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
255 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
256 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
257
258 /* Define the offset between two registers, one to be eliminated, and the other
259 its replacement, at the start of a routine. */
260 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
261 OFFSET = mcore_initial_elimination_offset (FROM, TO)
262
263 /* Define the classes of registers for register constraints in the
264 machine description. Also define ranges of constants.
265
266 One of the classes must always be named ALL_REGS and include all hard regs.
267 If there is more than one class, another class must be named NO_REGS
268 and contain no registers.
269
270 The name GENERAL_REGS must be the name of a class (or an alias for
271 another name such as ALL_REGS). This is the class of registers
272 that is allowed by "g" or "r" in a register constraint.
273 Also, registers outside this class are allocated only when
274 instructions express preferences for them.
275
276 The classes must be numbered in nondecreasing order; that is,
277 a larger-numbered class must never be contained completely
278 in a smaller-numbered class.
279
280 For any two classes, it is very desirable that there be another
281 class that represents their union. */
282
283 /* The MCore has only general registers. There are
284 also some special purpose registers: the T bit register, the
285 procedure Link and the Count Registers. */
286 enum reg_class
287 {
288 NO_REGS,
289 ONLYR1_REGS,
290 LRW_REGS,
291 GENERAL_REGS,
292 C_REGS,
293 ALL_REGS,
294 LIM_REG_CLASSES
295 };
296
297 #define N_REG_CLASSES (int) LIM_REG_CLASSES
298
299
300 /* Give names of register classes as strings for dump file. */
301 #define REG_CLASS_NAMES \
302 { \
303 "NO_REGS", \
304 "ONLYR1_REGS", \
305 "LRW_REGS", \
306 "GENERAL_REGS", \
307 "C_REGS", \
308 "ALL_REGS", \
309 }
310
311 /* Define which registers fit in which classes.
312 This is an initializer for a vector of HARD_REG_SET
313 of length N_REG_CLASSES. */
314
315 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
316 #define REG_CLASS_CONTENTS \
317 { \
318 {0x000000}, /* NO_REGS */ \
319 {0x000002}, /* ONLYR1_REGS */ \
320 {0x007FFE}, /* LRW_REGS */ \
321 {0x01FFFF}, /* GENERAL_REGS */ \
322 {0x020000}, /* C_REGS */ \
323 {0x0FFFFF} /* ALL_REGS */ \
324 }
325
326 /* The same information, inverted:
327 Return the class number of the smallest class containing
328 reg number REGNO. This could be a conditional expression
329 or could index an array. */
330
331 extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
332 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER ? regno_reg_class[REGNO] : NO_REGS)
333
334 /* When this hook returns true for MODE, the compiler allows
335 registers explicitly used in the rtl to be used as spill registers
336 but prevents the compiler from extending the lifetime of these
337 registers. */
338 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
339
340 /* The class value for index registers, and the one for base regs. */
341 #define INDEX_REG_CLASS NO_REGS
342 #define BASE_REG_CLASS GENERAL_REGS
343
344 /* Convenience wrappers around insn_const_int_ok_for_constraint. */
345 #define CONST_OK_FOR_I(VALUE) \
346 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_I)
347 #define CONST_OK_FOR_J(VALUE) \
348 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_J)
349 #define CONST_OK_FOR_L(VALUE) \
350 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_L)
351 #define CONST_OK_FOR_K(VALUE) \
352 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_K)
353 #define CONST_OK_FOR_M(VALUE) \
354 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_M)
355 #define CONST_OK_FOR_N(VALUE) \
356 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_N)
357 #define CONST_OK_FOR_O(VALUE) \
358 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_O)
359 #define CONST_OK_FOR_P(VALUE) \
360 insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_P)
361
362 /* Given an rtx X being reloaded into a reg required to be
363 in class CLASS, return the class of reg to actually use.
364 In general this is just CLASS; but on some machines
365 in some cases it is preferable to use a more restrictive class. */
366 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
367
368 /* Return the register class of a scratch register needed to copy IN into
369 or out of a register in CLASS in MODE. If it can be done directly,
370 NO_REGS is returned. */
371 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
372 mcore_secondary_reload_class (CLASS, MODE, X)
373
374 /* Return the maximum number of consecutive registers
375 needed to represent mode MODE in a register of class CLASS.
376
377 On MCore this is the size of MODE in words. */
378 #define CLASS_MAX_NREGS(CLASS, MODE) \
379 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
380
381 /* Stack layout; function entry, exit and calling. */
382
383 /* Define the number of register that can hold parameters.
384 These two macros are used only in other macro definitions below. */
385 #define NPARM_REGS 6
386 #define FIRST_PARM_REG 2
387 #define FIRST_RET_REG 2
388
389 /* Define this if pushing a word on the stack
390 makes the stack pointer a smaller address. */
391 #define STACK_GROWS_DOWNWARD 1
392
393 /* If defined, the maximum amount of space required for outgoing arguments
394 will be computed and placed into the variable
395 `crtl->outgoing_args_size'. No space will be pushed
396 onto the stack for each call; instead, the function prologue should
397 increase the stack frame size by this amount. */
398 #define ACCUMULATE_OUTGOING_ARGS 1
399
400 /* Offset of first parameter from the argument pointer register value. */
401 #define FIRST_PARM_OFFSET(FNDECL) 0
402
403 /* Define how to find the value returned by a function.
404 VALTYPE is the data type of the value (as a tree).
405 If the precise function being called is known, FUNC is its FUNCTION_DECL;
406 otherwise, FUNC is 0. */
407 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
408
409 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
410 we want to retain compatibility with older gcc versions. */
411 #define DEFAULT_PCC_STRUCT_RETURN 0
412
413 /* Define how to find the value returned by a library function
414 assuming the value has mode MODE. */
415 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG)
416
417 /* 1 if N is a possible register number for a function value.
418 On the MCore, only r4 can return results. */
419 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
420
421 /* 1 if N is a possible register number for function argument passing. */
422 #define FUNCTION_ARG_REGNO_P(REGNO) \
423 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
424
425 /* Define a data type for recording info about an argument list
426 during the scan of that argument list. This data type should
427 hold all necessary information about the function itself
428 and about the args processed so far, enough to enable macros
429 such as FUNCTION_ARG to determine where the next arg should go.
430
431 On MCore, this is a single integer, which is a number of words
432 of arguments scanned so far (including the invisible argument,
433 if any, which holds the structure-value-address).
434 Thus NARGREGS or more means all following args should go on the stack. */
435 #define CUMULATIVE_ARGS int
436
437 #define ROUND_ADVANCE(SIZE) \
438 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
439
440 /* Round a register number up to a proper boundary for an arg of mode
441 MODE.
442
443 We round to an even reg for things larger than a word. */
444 #define ROUND_REG(X, MODE) \
445 ((TARGET_8ALIGN \
446 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
447 ? ((X) + ((X) & 1)) : (X))
448
449
450 /* Initialize a variable CUM of type CUMULATIVE_ARGS
451 for a call to a function whose data type is FNTYPE.
452 For a library call, FNTYPE is 0.
453
454 On MCore, the offset always starts at 0: the first parm reg is always
455 the same reg. */
456 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
457 ((CUM) = 0)
458
459 /* Call the function profiler with a given profile label. */
460 #define FUNCTION_PROFILER(STREAM,LABELNO) \
461 { \
462 fprintf (STREAM, " trap 1\n"); \
463 fprintf (STREAM, " .align 2\n"); \
464 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \
465 }
466
467 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
468 the stack pointer does not matter. The value is tested only in
469 functions that have frame pointers.
470 No definition is equivalent to always zero. */
471 #define EXIT_IGNORE_STACK 0
472
473 /* Length in units of the trampoline for entering a nested function. */
474 #define TRAMPOLINE_SIZE 12
475
476 /* Alignment required for a trampoline in bits. */
477 #define TRAMPOLINE_ALIGNMENT 32
478
479 /* Macros to check register numbers against specific register classes. */
480
481 /* These assume that REGNO is a hard or pseudo reg number.
482 They give nonzero only if REGNO is a hard reg of the suitable class
483 or a pseudo reg currently allocated to a suitable hard reg.
484 Since they use reg_renumber, they are safe only once reg_renumber
485 has been allocated, which happens in reginfo.cc during register
486 allocation. */
487 #define REGNO_OK_FOR_BASE_P(REGNO) \
488 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
489
490 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
491
492 /* Maximum number of registers that can appear in a valid memory
493 address. */
494 #define MAX_REGS_PER_ADDRESS 1
495
496 /* Recognize any constant value that is a valid address. */
497 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
498
499 /* Specify the machine mode that this machine uses
500 for the index in the tablejump instruction. */
501 #define CASE_VECTOR_MODE SImode
502
503 /* 'char' is signed by default. */
504 #define DEFAULT_SIGNED_CHAR 0
505
506 #undef SIZE_TYPE
507 #define SIZE_TYPE "unsigned int"
508
509 #undef PTRDIFF_TYPE
510 #define PTRDIFF_TYPE "int"
511
512 #undef WCHAR_TYPE
513 #define WCHAR_TYPE "long int"
514
515 #undef WCHAR_TYPE_SIZE
516 #define WCHAR_TYPE_SIZE BITS_PER_WORD
517
518 /* Max number of bytes we can move from memory to memory
519 in one reasonably fast instruction. */
520 #define MOVE_MAX 4
521
522 /* Define if operations between registers always perform the operation
523 on the full register even if a narrower mode is specified. */
524 #define WORD_REGISTER_OPERATIONS 1
525
526 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
527 will either zero-extend or sign-extend. The value of this macro should
528 be the code that says which one of the two operations is implicitly
529 done, UNKNOWN if none. */
530 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
531
532 /* Nonzero if access to memory by bytes is slow and undesirable. */
533 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
534
535 /* Shift counts are truncated to 6-bits (0 to 63) instead of the expected
536 5-bits, so we cannot define SHIFT_COUNT_TRUNCATED to true for this
537 target. */
538 #define SHIFT_COUNT_TRUNCATED 0
539
540 /* Define this if addresses of constant functions
541 shouldn't be put through pseudo regs where they can be cse'd.
542 Desirable on machines where ordinary constants are expensive
543 but a CALL with constant address is cheap. */
544 /* Why is this defined??? -- dac */
545 #define NO_FUNCTION_CSE 1
546
547 /* The machine modes of pointers and functions. */
548 #define Pmode SImode
549 #define FUNCTION_MODE Pmode
550
551 /* Compute extra cost of moving data between one register class
552 and another. All register moves are cheap. */
553 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
554
555 /* Assembler output control. */
556 #define ASM_COMMENT_START "\t//"
557
558 #define ASM_APP_ON "// inline asm begin\n"
559 #define ASM_APP_OFF "// inline asm end\n"
560
561 #define FILE_ASM_OP "\t.file\n"
562
563 /* Switch to the text or data segment. */
564 #define TEXT_SECTION_ASM_OP "\t.text"
565 #define DATA_SECTION_ASM_OP "\t.data"
566
567 /* Switch into a generic section. */
568 #undef TARGET_ASM_NAMED_SECTION
569 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
570
571 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LK_REG)
572
573 /* This is how to output an insn to push a register on the stack.
574 It need not be very fast code. */
575 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
576 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \
577 reg_names[STACK_POINTER_REGNUM], \
578 (STACK_BOUNDARY / BITS_PER_UNIT), \
579 reg_names[REGNO], \
580 reg_names[STACK_POINTER_REGNUM])
581
582 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
583 #define REG_PUSH_LENGTH 2
584
585 /* This is how to output an insn to pop a register from the stack. */
586 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
587 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \
588 reg_names[REGNO], \
589 reg_names[STACK_POINTER_REGNUM], \
590 reg_names[STACK_POINTER_REGNUM], \
591 (STACK_BOUNDARY / BITS_PER_UNIT))
592
593
594 /* Output a reference to a label. */
595 #undef ASM_OUTPUT_LABELREF
596 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
597 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \
598 (* targetm.strip_name_encoding) (NAME))
599
600 /* This is how to output an assembler line
601 that says to advance the location counter
602 to a multiple of 2**LOG bytes. */
603 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
604 if ((LOG) != 0) \
605 fprintf (FILE, "\t.align\t%d\n", LOG)
606
607 #ifndef ASM_DECLARE_RESULT
608 #define ASM_DECLARE_RESULT(FILE, RESULT)
609 #endif
610
611 #define MULTIPLE_SYMBOL_SPACES 1
612
613 #define SUPPORTS_ONE_ONLY 1
614
615 /* A pair of macros to output things for the callgraph data.
616 VALUE means (to the tools that reads this info later):
617 0 a call from src to dst
618 1 the call is special (e.g. dst is "unknown" or "alloca")
619 2 the call is special (e.g., the src is a table instead of routine)
620
621 Frame sizes are augmented with timestamps to help later tools
622 differentiate between static entities with same names in different
623 files. */
624 extern long mcore_current_compilation_timestamp;
625 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
626 do \
627 { \
628 if (mcore_current_compilation_timestamp == 0) \
629 mcore_current_compilation_timestamp = time (0); \
630 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \
631 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
632 } \
633 while (0)
634
635 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
636 do \
637 { \
638 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \
639 (SRCNAME), (DSTNAME), (VALUE)); \
640 } \
641 while (0)
642
643 /* Globalizing directive for a label. */
644 #define GLOBAL_ASM_OP "\t.export\t"
645
646 /* The prefix to add to user-visible assembler symbols. */
647 #undef USER_LABEL_PREFIX
648 #define USER_LABEL_PREFIX ""
649
650 /* Make an internal label into a string. */
651 #undef ASM_GENERATE_INTERNAL_LABEL
652 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
653 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM)
654
655 /* Jump tables must be 32 bit aligned. */
656 #undef ASM_OUTPUT_CASE_LABEL
657 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
658 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM);
659
660 /* Output a relative address. Not needed since jump tables are absolute
661 but we must define it anyway. */
662 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
663 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
664
665 /* Output an element of a dispatch table. */
666 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
667 fprintf (STREAM, "\t.long\t.L%d\n", VALUE)
668
669 /* Output various types of constants. */
670
671 /* This is how to output an assembler line
672 that says to advance the location counter by SIZE bytes. */
673 #undef ASM_OUTPUT_SKIP
674 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
675 fprintf (FILE, "\t.fill %d, 1\n", (int)(SIZE))
676
677 /* This says how to output an assembler line
678 to define a global common symbol, with alignment information. */
679 /* XXX - for now we ignore the alignment. */
680 #undef ASM_OUTPUT_ALIGNED_COMMON
681 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
682 do \
683 { \
684 if (mcore_dllexport_name_p (NAME)) \
685 MCORE_EXPORT_NAME (FILE, NAME); \
686 if (! mcore_dllimport_name_p (NAME)) \
687 { \
688 fputs ("\t.comm\t", FILE); \
689 assemble_name (FILE, NAME); \
690 fprintf (FILE, ",%lu\n", (unsigned long)(SIZE)); \
691 } \
692 } \
693 while (0)
694
695 /* This says how to output an assembler line
696 to define a local common symbol.... */
697 #undef ASM_OUTPUT_LOCAL
698 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
699 (fputs ("\t.lcomm\t", FILE), \
700 assemble_name (FILE, NAME), \
701 fprintf (FILE, ",%d\n", (int)SIZE))
702
703 /* ... and how to define a local common symbol whose alignment
704 we wish to specify. ALIGN comes in as bits, we have to turn
705 it into bytes. */
706 #undef ASM_OUTPUT_ALIGNED_LOCAL
707 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
708 do \
709 { \
710 fputs ("\t.bss\t", (FILE)); \
711 assemble_name ((FILE), (NAME)); \
712 fprintf ((FILE), ",%d,%d\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
713 } \
714 while (0)
715
716 #endif /* ! GCC_MCORE_H */