1 /* Target Definitions for R8C/M16C/M32C
2 Copyright (C) 2005-2023 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef GCC_M32C_H
22 #define GCC_M32C_H
23
24 /* Controlling the Compilation Driver, `gcc'. */
25
26 #undef STARTFILE_SPEC
27 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
28
29 #undef ENDFILE_SPEC
30 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
31
32 #undef LINK_SPEC
33 #define LINK_SPEC "%{h*} %{v:-V} \
34 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
35
36 /* There are four CPU series we support, but they basically break down
37 into two families - the R8C/M16C families, with 16-bit address
38 registers and one set of opcodes, and the M32CM/M32C group, with
39 24-bit address registers and a different set of opcodes. The
40 assembler doesn't care except for which opcode set is needed; the
41 big difference is in the memory maps, which we cover in
42 LIB_SPEC. */
43
44 #undef ASM_SPEC
45 #define ASM_SPEC "\
46 %{mcpu=r8c:--m16c} \
47 %{mcpu=m16c:--m16c} \
48 %{mcpu=m32cm:--m32c} \
49 %{mcpu=m32c:--m32c} "
50
51 /* The default is R8C hardware. We support a simulator, which has its
52 own libgloss and link map, plus one default link map for each chip
53 family. Most of the logic here is making sure we do the right
54 thing when no CPU is specified, which defaults to R8C. */
55 #undef LIB_SPEC
56 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \
57 %{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
58 %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
59 %{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \
60 %{mcpu=m32cm:%Tm32cm.ld} \
61 %{mcpu=m32c:%Tm32c.ld} \
62 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
63 "
64
65 /* Run-time Target Specification */
66
67 /* Nothing unusual here. */
68 #define TARGET_CPU_CPP_BUILTINS() \
69 { \
70 builtin_assert ("cpu=m32c"); \
71 builtin_assert ("machine=m32c"); \
72 builtin_define ("__m32c__=1"); \
73 if (TARGET_R8C) \
74 builtin_define ("__r8c_cpu__=1"); \
75 if (TARGET_M16C) \
76 builtin_define ("__m16c_cpu__=1"); \
77 if (TARGET_M32CM) \
78 builtin_define ("__m32cm_cpu__=1"); \
79 if (TARGET_M32C) \
80 builtin_define ("__m32c_cpu__=1"); \
81 }
82
83 /* The pragma handlers need to know if we've started processing
84 functions yet, as the memregs pragma should only be given at the
85 beginning of the file. This variable starts off TRUE and later
86 becomes FALSE. */
87 extern int ok_to_change_target_memregs;
88
89 /* TARGET_CPU is a multi-way option set in m32c.opt. While we could
90 use enums or defines for this, this and m32c.opt are the only
91 places that know (or care) what values are being used. */
92 #define TARGET_R8C (target_cpu == 'r')
93 #define TARGET_M16C (target_cpu == '6')
94 #define TARGET_M32CM (target_cpu == 'm')
95 #define TARGET_M32C (target_cpu == '3')
96
97 /* Address register sizes. Warning: these are used all over the place
98 to select between the two CPU families in general. */
99 #define TARGET_A16 (TARGET_R8C || TARGET_M16C)
100 #define TARGET_A24 (TARGET_M32CM || TARGET_M32C)
101
102 /* Defining data structures for per-function information */
103
104 typedef struct GTY (()) machine_function
105 {
106 /* How much we adjust the stack when returning from an exception
107 handler. */
108 rtx eh_stack_adjust;
109
110 /* TRUE if the current function is an interrupt handler. */
111 int is_interrupt;
112
113 /* TRUE if the current function is a leaf function. Currently, this
114 only affects saving $a0 in interrupt functions. */
115 int is_leaf;
116
117 /* Bitmask that keeps track of which registers are used in an
118 interrupt function, so we know which ones need to be saved and
119 restored. */
120 int intr_pushm;
121 /* Likewise, one element for each memreg that needs to be saved. */
122 char intr_pushmem[16];
123
124 /* TRUE if the current function can use a simple RTS to return, instead
125 of the longer ENTER/EXIT pair. */
126 int use_rts;
127 }
128 machine_function;
129
130 #define INIT_EXPANDERS m32c_init_expanders ()
131
132 /* Storage Layout */
133
134 #define BITS_BIG_ENDIAN 0
135 #define BYTES_BIG_ENDIAN 0
136 #define WORDS_BIG_ENDIAN 0
137
138 /* We can do QI, HI, and SI operations pretty much equally well, but
139 GCC expects us to have a "native" format, so we pick the one that
140 matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16
141 is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
142 24-bit pointers are stored in 32-bit words. */
143 #define UNITS_PER_WORD 2
144 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
145 #define POINTERS_EXTEND_UNSIGNED 1
146 /* We have a problem with libgcc2. It only defines two versions of
147 each function, one for "int" and one for "long long". Ie it assumes
148 that "sizeof (int) == sizeof (long)". For the M32C this is not true
149 and we need a third set of functions. We explicitly define
150 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
151 to get the SI and DI versions from the libgcc2.c sources, and we
152 provide our own set of HI functions in m32c-lib2.c, which is why this
153 definition is surrounded by #ifndef..#endif. */
154 #ifndef LIBGCC2_UNITS_PER_WORD
155 #define LIBGCC2_UNITS_PER_WORD 4
156 #endif
157
158 /* These match the alignment enforced by the two types of stack operations. */
159 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
160 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
161
162 /* We do this because we care more about space than about speed. For
163 the chips with 16-bit busses, we could set these to 16 if
164 desired. */
165 #define FUNCTION_BOUNDARY 8
166 #define BIGGEST_ALIGNMENT 8
167
168 /* Since we have a maximum structure alignment of 8 there
169 is no need to enforce any alignment of bitfield types. */
170 #undef PCC_BITFIELD_TYPE_MATTERS
171 #define PCC_BITFIELD_TYPE_MATTERS 0
172
173 #define STRICT_ALIGNMENT 0
174 #define SLOW_BYTE_ACCESS 1
175
176 /* Layout of Source Language Data Types */
177
178 #define INT_TYPE_SIZE 16
179 #define SHORT_TYPE_SIZE 16
180 #define LONG_TYPE_SIZE 32
181 #define LONG_LONG_TYPE_SIZE 64
182
183 #define FLOAT_TYPE_SIZE 32
184 #define DOUBLE_TYPE_SIZE 64
185 #define LONG_DOUBLE_TYPE_SIZE 64
186
187 #define DEFAULT_SIGNED_CHAR 1
188
189 #undef PTRDIFF_TYPE
190 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
191
192 #undef UINTPTR_TYPE
193 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
194
195 #undef SIZE_TYPE
196 #define SIZE_TYPE "unsigned int"
197
198 #undef WCHAR_TYPE
199 #define WCHAR_TYPE "long int"
200
201 #undef WCHAR_TYPE_SIZE
202 #define WCHAR_TYPE_SIZE 32
203
204 /* REGISTER USAGE */
205
206 /* Register Basics */
207
208 /* Register layout:
209
210 [r0h][r0l] $r0 (16 bits, or two 8-bit halves)
211 [--------] $r2 (16 bits)
212 [r1h][r1l] $r1 (16 bits, or two 8-bit halves)
213 [--------] $r3 (16 bits)
214 [---][--------] $a0 (might be 24 bits)
215 [---][--------] $a1 (might be 24 bits)
216 [---][--------] $sb (might be 24 bits)
217 [---][--------] $fb (might be 24 bits)
218 [---][--------] $sp (might be 24 bits)
219 [-------------] $pc (20 or 24 bits)
220 [---] $flg (CPU flags)
221 [---][--------] $argp (virtual)
222 [--------] $mem0 (all 16 bits)
223 . . .
224 [--------] $mem14
225 */
226
227 #define FIRST_PSEUDO_REGISTER 20
228
229 /* Note that these two tables are modified based on which CPU family
230 you select; see m32c_conditional_register_usage for details. */
231
232 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
233 #define FIXED_REGISTERS { 0, 0, 0, 0, \
234 0, 0, 1, 0, \
235 1, 1, 0, 1, \
236 0, 0, 0, 0, 0, 0, 0, 0 }
237 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
238 1, 1, 1, 0, \
239 1, 1, 1, 1, \
240 1, 1, 1, 1, 1, 1, 1, 1 }
241
242 /* The *_REGNO theme matches m32c.md and most register number
243 arguments; the PC_REGNUM is the odd one out. */
244 #ifndef PC_REGNO
245 #define PC_REGNO 9
246 #endif
247 #define PC_REGNUM PC_REGNO
248
249 /* Order of Allocation of Registers */
250
251 #define REG_ALLOC_ORDER { \
252 0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
253 12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */ \
254 6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
255
256 /* How Values Fit in Registers */
257
258 #define AVOID_CCMODE_COPIES
259
260 /* Register Classes */
261
262 /* Most registers are special purpose in some form or another, so this
263 table is pretty big. Class names are used for constraints also;
264 for example the HL_REGS class (HL below) is "Rhl" in the md files.
265 See m32c_reg_class_from_constraint for the mapping. There's some
266 duplication so that we can better isolate the reason for using
267 constraints in the md files from the actual registers used; for
268 example we may want to exclude a1a0 from SI_REGS in the future,
269 without precluding their use as HImode registers. */
270
271 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
272 /* mmPAR */
273 #define REG_CLASS_CONTENTS \
274 { { 0x00000000 }, /* NO */\
275 { 0x00000100 }, /* SP - sp */\
276 { 0x00000080 }, /* FB - fb */\
277 { 0x00000040 }, /* SB - sb */\
278 { 0x000001c0 }, /* CR - sb fb sp */\
279 { 0x00000001 }, /* R0 - r0 */\
280 { 0x00000004 }, /* R1 - r1 */\
281 { 0x00000002 }, /* R2 - r2 */\
282 { 0x00000008 }, /* R3 - r3 */\
283 { 0x00000003 }, /* R02 - r0r2 */\
284 { 0x0000000c }, /* R13 - r1r3 */\
285 { 0x00000005 }, /* HL - r0 r1 */\
286 { 0x0000000a }, /* R23 - r2 r3 */\
287 { 0x0000000f }, /* R03 - r0r2 r1r3 */\
288 { 0x00000010 }, /* A0 - a0 */\
289 { 0x00000020 }, /* A1 - a1 */\
290 { 0x00000030 }, /* A - a0 a1 */\
291 { 0x000000f0 }, /* AD - a0 a1 sb fp */\
292 { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\
293 { 0x00000033 }, /* R02A - r0r2 a0 a1 */ \
294 { 0x0000003f }, /* RA - r0 r1 r2 r3 a0 a1 */\
295 { 0x0000007f }, /* GENERAL */\
296 { 0x00000400 }, /* FLG */\
297 { 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\
298 { 0x000ff000 }, /* MEM */\
299 { 0x000ff003 }, /* R02_A_MEM */\
300 { 0x000ff005 }, /* A_HL_MEM */\
301 { 0x000ff00c }, /* R1_R3_A_MEM */\
302 { 0x000ff00f }, /* R03_MEM */\
303 { 0x000ff03f }, /* A_HI_MEM */\
304 { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
305 { 0x000ff5ff }, /* ALL */\
306 }
307
308 #define QI_REGS HL_REGS
309 #define HI_REGS RA_REGS
310 #define SI_REGS R03_REGS
311 #define DI_REGS R03_REGS
312
313 enum reg_class
314 {
315 NO_REGS,
316 SP_REGS,
317 FB_REGS,
318 SB_REGS,
319 CR_REGS,
320 R0_REGS,
321 R1_REGS,
322 R2_REGS,
323 R3_REGS,
324 R02_REGS,
325 R13_REGS,
326 HL_REGS,
327 R23_REGS,
328 R03_REGS,
329 A0_REGS,
330 A1_REGS,
331 A_REGS,
332 AD_REGS,
333 PS_REGS,
334 R02A_REGS,
335 RA_REGS,
336 GENERAL_REGS,
337 FLG_REGS,
338 HC_REGS,
339 MEM_REGS,
340 R02_A_MEM_REGS,
341 A_HL_MEM_REGS,
342 R1_R3_A_MEM_REGS,
343 R03_MEM_REGS,
344 A_HI_MEM_REGS,
345 A_AD_CR_MEM_SI_REGS,
346 ALL_REGS,
347 LIM_REG_CLASSES
348 };
349
350 #define N_REG_CLASSES LIM_REG_CLASSES
351
352 #define REG_CLASS_NAMES {\
353 "NO_REGS", \
354 "SP_REGS", \
355 "FB_REGS", \
356 "SB_REGS", \
357 "CR_REGS", \
358 "R0_REGS", \
359 "R1_REGS", \
360 "R2_REGS", \
361 "R3_REGS", \
362 "R02_REGS", \
363 "R13_REGS", \
364 "HL_REGS", \
365 "R23_REGS", \
366 "R03_REGS", \
367 "A0_REGS", \
368 "A1_REGS", \
369 "A_REGS", \
370 "AD_REGS", \
371 "PS_REGS", \
372 "R02A_REGS", \
373 "RA_REGS", \
374 "GENERAL_REGS", \
375 "FLG_REGS", \
376 "HC_REGS", \
377 "MEM_REGS", \
378 "R02_A_MEM_REGS", \
379 "A_HL_MEM_REGS", \
380 "R1_R3_A_MEM_REGS", \
381 "R03_MEM_REGS", \
382 "A_HI_MEM_REGS", \
383 "A_AD_CR_MEM_SI_REGS", \
384 "ALL_REGS", \
385 }
386
387 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
388
389 /* We support simple displacements off address registers, nothing else. */
390 #define BASE_REG_CLASS A_REGS
391 #define INDEX_REG_CLASS NO_REGS
392
393 /* We primarily use the new "long" constraint names, with the initial
394 letter classifying the constraint type and following letters
395 specifying which. The types are:
396
397 I - integer values
398 R - register classes
399 S - memory references (M was used)
400 A - addresses (currently unused)
401 */
402
403 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
404 #define REGNO_OK_FOR_INDEX_P(NUM) 0
405
406 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
407 (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
408
409 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
410 (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
411
412 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
413
414 /* STACK AND CALLING */
415
416 /* Frame Layout */
417
418 /* Standard push/pop stack, no surprises here. */
419
420 #define STACK_GROWS_DOWNWARD 1
421 #define STACK_PUSH_CODE PRE_DEC
422 #define FRAME_GROWS_DOWNWARD 1
423
424 #define FIRST_PARM_OFFSET(F) 0
425
426 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
427
428 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
429 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
430
431 /* Exception Handling Support */
432
433 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
434 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
435
436 /* Registers That Address the Stack Frame */
437
438 #ifndef FP_REGNO
439 #define FP_REGNO 7
440 #endif
441 #ifndef SP_REGNO
442 #define SP_REGNO 8
443 #endif
444 #define AP_REGNO 11
445
446 #define STACK_POINTER_REGNUM SP_REGNO
447 #define FRAME_POINTER_REGNUM FP_REGNO
448 #define ARG_POINTER_REGNUM AP_REGNO
449
450 /* The static chain must be pointer-capable. */
451 #define STATIC_CHAIN_REGNUM A0_REGNO
452
453 #define DWARF_FRAME_REGISTERS 20
454 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
455 #define DEBUGGER_REGNO(N) m32c_dwarf_frame_regnum (N)
456
457 #undef ASM_PREFERRED_EH_DATA_FORMAT
458 /* This is the same as the default in practice, except that by making
459 it explicit we tell binutils what size pointers to use. */
460 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
461 (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
462
463 /* Eliminating Frame Pointer and Arg Pointer */
464
465 #define ELIMINABLE_REGS \
466 {{AP_REGNO, SP_REGNO}, \
467 {AP_REGNO, FB_REGNO}, \
468 {FB_REGNO, SP_REGNO}}
469
470 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
471 (VAR) = m32c_initial_elimination_offset(FROM,TO)
472
473 /* Passing Function Arguments on the Stack */
474
475 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
476 #define CALL_POPS_ARGS(C) 0
477
478 /* Passing Arguments in Registers */
479
480 typedef struct m32c_cumulative_args
481 {
482 /* For address of return value buffer (structures are returned by
483 passing the address of a buffer as an invisible first argument.
484 This identifies it). If set, the current parameter will be put
485 on the stack, regardless of type. */
486 int force_mem;
487 /* First parm is 1, parm 0 is hidden pointer for returning
488 aggregates. */
489 int parm_num;
490 } m32c_cumulative_args;
491
492 #define CUMULATIVE_ARGS m32c_cumulative_args
493 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
494 m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
495 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
496
497 /* How Large Values Are Returned */
498
499 #define DEFAULT_PCC_STRUCT_RETURN 1
500
501 /* Function Entry and Exit */
502
503 #define EXIT_IGNORE_STACK 0
504 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
505 #define EH_USES(REGNO) 0 /* FIXME */
506
507 /* Generating Code for Profiling */
508
509 #define FUNCTION_PROFILER(FILE,LABELNO)
510
511 /* Implementing the Varargs Macros */
512
513 /* Trampolines for Nested Functions */
514
515 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
516 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
517
518 /* Addressing Modes */
519
520 #define HAVE_PRE_DECREMENT 1
521 #define HAVE_POST_INCREMENT 1
522 #define MAX_REGS_PER_ADDRESS 1
523
524 /* This is passed to the macros below, so that they can be implemented
525 in m32c.cc. */
526 #ifdef REG_OK_STRICT
527 #define REG_OK_STRICT_V 1
528 #else
529 #define REG_OK_STRICT_V 0
530 #endif
531
532 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
533 #define REG_OK_FOR_INDEX_P(X) 0
534
535 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
536
537 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
538 if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
539 goto WIN;
540
541 /* Address spaces. */
542 #define ADDR_SPACE_FAR 1
543
544
545 /* Condition Code Status */
546
547 #define REVERSIBLE_CC_MODE(MODE) 1
548
549 /* Dividing the Output into Sections (Texts, Data, ...) */
550
551 #define TEXT_SECTION_ASM_OP ".text"
552 #define DATA_SECTION_ASM_OP ".data"
553 #define BSS_SECTION_ASM_OP ".bss"
554
555 #define CTOR_LIST_BEGIN
556 #define CTOR_LIST_END
557 #define DTOR_LIST_BEGIN
558 #define DTOR_LIST_END
559 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
560 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
561 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
562 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
563
564 /* The Overall Framework of an Assembler File */
565
566 #define ASM_COMMENT_START ";"
567 #define ASM_APP_ON ""
568 #define ASM_APP_OFF ""
569
570 /* Output and Generation of Labels */
571
572 #define GLOBAL_ASM_OP "\t.global\t"
573
574 /* Output of Assembler Instructions */
575
576 #define REGISTER_NAMES { \
577 "r0", "r2", "r1", "r3", \
578 "a0", "a1", "sb", "fb", "sp", \
579 "pc", "flg", "argp", \
580 "mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \
581 }
582
583 #define ADDITIONAL_REGISTER_NAMES { \
584 {"r0l", 0}, \
585 {"r1l", 2}, \
586 {"r0r2", 0}, \
587 {"r1r3", 2}, \
588 {"a0a1", 4}, \
589 {"r0r2r1r3", 0} }
590
591 #undef USER_LABEL_PREFIX
592 #define USER_LABEL_PREFIX "_"
593
594 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
595 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
596
597 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
598 m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
599
600 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
601 m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
602
603
604 /* Output of Dispatch Tables */
605
606 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
607 fprintf (S, "\t.word L%d\n", V)
608
609 /* Assembler Commands for Exception Regions */
610
611 #define DWARF_CIE_DATA_ALIGNMENT -1
612
613 /* Assembler Commands for Alignment */
614
615 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
616 fprintf (STREAM, "\t.p2align\t%d\n", POWER);
617
618 /* Controlling Debugging Information Format */
619
620 #define DWARF2_ADDR_SIZE 4
621
622 /* Miscellaneous Parameters */
623
624 #define HAS_LONG_COND_BRANCH false
625 #define HAS_LONG_UNCOND_BRANCH true
626 #define CASE_VECTOR_MODE SImode
627 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
628
629 #define MOVE_MAX 4
630
631 #define STORE_FLAG_VALUE 1
632
633 /* 16- or 24-bit pointers */
634 #define Pmode (TARGET_A16 ? HImode : PSImode)
635 #define FUNCTION_MODE QImode
636
637 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
638
639 #endif