1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2023 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
19
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
24
25 /* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
27
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
30
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
33
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
39
40 /* Redefines for option macros. */
41
42 #define TARGET_CMPXCHG16B TARGET_CX16
43 #define TARGET_CMPXCHG16B_P(x) TARGET_CX16_P(x)
44
45 #define TARGET_LP64 TARGET_ABI_64
46 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
47 #define TARGET_X32 TARGET_ABI_X32
48 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
49 #define TARGET_16BIT TARGET_CODE16
50 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
51
52 #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
53
54 #include "config/vxworks-dummy.h"
55
56 #include "config/i386/i386-opts.h"
57
58 #define MAX_STRINGOP_ALGS 4
59
60 /* Specify what algorithm to use for stringops on known size.
61 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
62 known at compile time or estimated via feedback, the SIZE array
63 is walked in order until MAX is greater then the estimate (or -1
64 means infinity). Corresponding ALG is used then.
65 When NOALIGN is true the code guaranting the alignment of the memory
66 block is skipped.
67
68 For example initializer:
69 {{256, loop}, {-1, rep_prefix_4_byte}}
70 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
71 be used otherwise. */
72 struct stringop_algs
73 {
74 const enum stringop_alg unknown_size;
75 const struct stringop_strategy {
76 /* Several older compilers delete the default constructor because of the
77 const entries (see PR100246). Manually specifying a CTOR works around
78 this issue. Since this header is used by code compiled with the C
79 compiler we must guard the addition. */
80 #ifdef __cplusplus
81 constexpr
82 stringop_strategy (int _max = -1, enum stringop_alg _alg = libcall,
83 int _noalign = false)
84 : max (_max), alg (_alg), noalign (_noalign) {}
85 #endif
86 const int max;
87 const enum stringop_alg alg;
88 int noalign;
89 } size [MAX_STRINGOP_ALGS];
90 };
91
92 /* Analog of COSTS_N_INSNS when optimizing for size. */
93 #ifndef COSTS_N_BYTES
94 #define COSTS_N_BYTES(N) ((N) * 2)
95 #endif
96
97 /* Define the specific costs for a given cpu. NB: hard_register is used
98 by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute
99 hard register move costs by register allocator. Relative costs of
100 pseudo register load and store versus pseudo register moves in RTL
101 expressions for TARGET_RTX_COSTS can be different from relative
102 costs of hard registers to get the most efficient operations with
103 pseudo registers. */
104
105 struct processor_costs {
106 /* Costs used by register allocator. integer->integer register move
107 cost is 2. */
108 struct
109 {
110 const int movzbl_load; /* cost of loading using movzbl */
111 const int int_load[3]; /* cost of loading integer registers
112 in QImode, HImode and SImode relative
113 to reg-reg move (2). */
114 const int int_store[3]; /* cost of storing integer register
115 in QImode, HImode and SImode */
116 const int fp_move; /* cost of reg,reg fld/fst */
117 const int fp_load[3]; /* cost of loading FP register
118 in SFmode, DFmode and XFmode */
119 const int fp_store[3]; /* cost of storing FP register
120 in SFmode, DFmode and XFmode */
121 const int mmx_move; /* cost of moving MMX register. */
122 const int mmx_load[2]; /* cost of loading MMX register
123 in SImode and DImode */
124 const int mmx_store[2]; /* cost of storing MMX register
125 in SImode and DImode */
126 const int xmm_move; /* cost of moving XMM register. */
127 const int ymm_move; /* cost of moving XMM register. */
128 const int zmm_move; /* cost of moving XMM register. */
129 const int sse_load[5]; /* cost of loading SSE register
130 in 32bit, 64bit, 128bit, 256bit and 512bit */
131 const int sse_store[5]; /* cost of storing SSE register
132 in SImode, DImode and TImode. */
133 const int sse_to_integer; /* cost of moving SSE register to integer. */
134 const int integer_to_sse; /* cost of moving integer register to SSE. */
135 const int mask_to_integer; /* cost of moving mask register to integer. */
136 const int integer_to_mask; /* cost of moving integer register to mask. */
137 const int mask_load[3]; /* cost of loading mask registers
138 in QImode, HImode and SImode. */
139 const int mask_store[3]; /* cost of storing mask register
140 in QImode, HImode and SImode. */
141 const int mask_move; /* cost of moving mask register. */
142 } hard_register;
143
144 const int add; /* cost of an add instruction */
145 const int lea; /* cost of a lea instruction */
146 const int shift_var; /* variable shift costs */
147 const int shift_const; /* constant shift costs */
148 const int mult_init[5]; /* cost of starting a multiply
149 in QImode, HImode, SImode, DImode, TImode*/
150 const int mult_bit; /* cost of multiply per each bit set */
151 const int divide[5]; /* cost of a divide/mod
152 in QImode, HImode, SImode, DImode, TImode*/
153 int movsx; /* The cost of movsx operation. */
154 int movzx; /* The cost of movzx operation. */
155 const int large_insn; /* insns larger than this cost more */
156 const int move_ratio; /* The threshold of number of scalar
157 memory-to-memory move insns. */
158 const int clear_ratio; /* The threshold of number of scalar
159 memory clearing insns. */
160 const int int_load[3]; /* cost of loading integer registers
161 in QImode, HImode and SImode relative
162 to reg-reg move (2). */
163 const int int_store[3]; /* cost of storing integer register
164 in QImode, HImode and SImode */
165 const int sse_load[5]; /* cost of loading SSE register
166 in 32bit, 64bit, 128bit, 256bit and 512bit */
167 const int sse_store[5]; /* cost of storing SSE register
168 in 32bit, 64bit, 128bit, 256bit and 512bit */
169 const int sse_unaligned_load[5];/* cost of unaligned load. */
170 const int sse_unaligned_store[5];/* cost of unaligned store. */
171 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
172 zmm_move;
173 const int sse_to_integer; /* cost of moving SSE register to integer. */
174 const int gather_static, gather_per_elt; /* Cost of gather load is computed
175 as static + per_item * nelts. */
176 const int scatter_static, scatter_per_elt; /* Cost of gather store is
177 computed as static + per_item * nelts. */
178 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
179 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
180 const int prefetch_block; /* bytes moved to cache for prefetch. */
181 const int simultaneous_prefetches; /* number of parallel prefetch
182 operations. */
183 const int branch_cost; /* Default value for BRANCH_COST. */
184 const int fadd; /* cost of FADD and FSUB instructions. */
185 const int fmul; /* cost of FMUL instruction. */
186 const int fdiv; /* cost of FDIV instruction. */
187 const int fabs; /* cost of FABS instruction. */
188 const int fchs; /* cost of FCHS instruction. */
189 const int fsqrt; /* cost of FSQRT instruction. */
190 /* Specify what algorithm
191 to use for stringops on unknown size. */
192 const int sse_op; /* cost of cheap SSE instruction. */
193 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
194 const int mulss; /* cost of MULSS instructions. */
195 const int mulsd; /* cost of MULSD instructions. */
196 const int fmass; /* cost of FMASS instructions. */
197 const int fmasd; /* cost of FMASD instructions. */
198 const int divss; /* cost of DIVSS instructions. */
199 const int divsd; /* cost of DIVSD instructions. */
200 const int sqrtss; /* cost of SQRTSS instructions. */
201 const int sqrtsd; /* cost of SQRTSD instructions. */
202 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
203 /* Specify reassociation width for integer,
204 fp, vector integer and vector fp
205 operations. Generally should correspond
206 to number of instructions executed in
207 parallel. See also
208 ix86_reassociation_width. */
209 struct stringop_algs *memcpy, *memset;
210 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
211 cost model. */
212 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
213 vectorizer cost model. */
214
215 /* The "0:0:8" label alignment specified for some processors generates
216 secondary 8-byte alignment only for those label/jump/loop targets
217 which have primary alignment. */
218 const char *const align_loop; /* Loop alignment. */
219 const char *const align_jump; /* Jump alignment. */
220 const char *const align_label; /* Label alignment. */
221 const char *const align_func; /* Function alignment. */
222
223 const unsigned small_unroll_ninsns; /* Insn count limit for small loop
224 to be unrolled. */
225 const unsigned small_unroll_factor; /* Unroll factor for small loop to
226 be unrolled. */
227 };
228
229 extern const struct processor_costs *ix86_cost;
230 extern const struct processor_costs ix86_size_cost;
231
232 #define ix86_cur_cost() \
233 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
234
235 /* Macros used in the machine description to test the flags. */
236
237 /* configure can arrange to change it. */
238
239 #ifndef TARGET_CPU_DEFAULT
240 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
241 #endif
242
243 #ifndef TARGET_FPMATH_DEFAULT
244 #define TARGET_FPMATH_DEFAULT \
245 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
246 #endif
247
248 #ifndef TARGET_FPMATH_DEFAULT_P
249 #define TARGET_FPMATH_DEFAULT_P(x) \
250 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
251 #endif
252
253 /* If the i387 is disabled or -miamcu is used , then do not return
254 values in it. */
255 #define TARGET_FLOAT_RETURNS_IN_80387 \
256 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
257 #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
258 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
259
260 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
261 compile-time constant. */
262 #ifdef IN_LIBGCC2
263 #undef TARGET_64BIT
264 #ifdef __x86_64__
265 #define TARGET_64BIT 1
266 #else
267 #define TARGET_64BIT 0
268 #endif
269 #else
270 #ifndef TARGET_BI_ARCH
271 #undef TARGET_64BIT
272 #undef TARGET_64BIT_P
273 #if TARGET_64BIT_DEFAULT
274 #define TARGET_64BIT 1
275 #define TARGET_64BIT_P(x) 1
276 #else
277 #define TARGET_64BIT 0
278 #define TARGET_64BIT_P(x) 0
279 #endif
280 #endif
281 #endif
282
283 #define HAS_LONG_COND_BRANCH 1
284 #define HAS_LONG_UNCOND_BRANCH 1
285
286 #define TARGET_CPU_P(CPU) (ix86_tune == PROCESSOR_ ## CPU)
287
288 /* Feature tests against the various tunings. */
289 enum ix86_tune_indices {
290 #undef DEF_TUNE
291 #define DEF_TUNE(tune, name, selector) tune,
292 #include "x86-tune.def"
293 #undef DEF_TUNE
294 X86_TUNE_LAST
295 };
296
297 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
298
299 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
300 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
301 #define TARGET_ZERO_EXTEND_WITH_AND \
302 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
303 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
304 #define TARGET_BRANCH_PREDICTION_HINTS \
305 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
306 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
307 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
308 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
309 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
310 #define TARGET_PARTIAL_FLAG_REG_STALL \
311 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
312 #define TARGET_LCP_STALL \
313 ix86_tune_features[X86_TUNE_LCP_STALL]
314 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
315 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
316 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
317 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
318 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
319 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
320 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
321 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
322 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
323 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
324 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
325 #define TARGET_PREFER_KNOWN_REP_MOVSB_STOSB \
326 ix86_tune_features[X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB]
327 #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
328 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
329 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
330 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
331 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
332 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
333 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
334 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
335 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
336 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
337 #define TARGET_INTEGER_DFMODE_MOVES \
338 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
339 #define TARGET_PARTIAL_REG_DEPENDENCY \
340 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
341 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
342 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
343 #define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \
344 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY]
345 #define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \
346 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY]
347 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
348 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
349 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
350 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
351 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
352 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
353 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
354 #define TARGET_SSE_TYPELESS_STORES \
355 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
356 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
357 #define TARGET_MEMORY_MISMATCH_STALL \
358 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
359 #define TARGET_PROLOGUE_USING_MOVE \
360 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
361 #define TARGET_EPILOGUE_USING_MOVE \
362 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
363 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
364 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
365 #define TARGET_INTER_UNIT_MOVES_TO_VEC \
366 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
367 #define TARGET_INTER_UNIT_MOVES_FROM_VEC \
368 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
369 #define TARGET_INTER_UNIT_CONVERSIONS \
370 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
371 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
372 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
373 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
374 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
375 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
376 #define TARGET_PAD_SHORT_FUNCTION \
377 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
378 #define TARGET_EXT_80387_CONSTANTS \
379 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
380 #define TARGET_AVOID_VECTOR_DECODE \
381 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
382 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
383 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
384 #define TARGET_SLOW_IMUL_IMM32_MEM \
385 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
386 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
387 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
388 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
389 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
390 #define TARGET_USE_VECTOR_FP_CONVERTS \
391 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
392 #define TARGET_USE_VECTOR_CONVERTS \
393 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
394 #define TARGET_SLOW_PSHUFB \
395 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
396 #define TARGET_AVOID_4BYTE_PREFIXES \
397 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
398 #define TARGET_USE_GATHER_2PARTS \
399 ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS]
400 #define TARGET_USE_SCATTER_2PARTS \
401 ix86_tune_features[X86_TUNE_USE_SCATTER_2PARTS]
402 #define TARGET_USE_GATHER_4PARTS \
403 ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS]
404 #define TARGET_USE_SCATTER_4PARTS \
405 ix86_tune_features[X86_TUNE_USE_SCATTER_4PARTS]
406 #define TARGET_USE_GATHER \
407 ix86_tune_features[X86_TUNE_USE_GATHER]
408 #define TARGET_USE_SCATTER \
409 ix86_tune_features[X86_TUNE_USE_SCATTER]
410 #define TARGET_FUSE_CMP_AND_BRANCH_32 \
411 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
412 #define TARGET_FUSE_CMP_AND_BRANCH_64 \
413 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
414 #define TARGET_FUSE_CMP_AND_BRANCH \
415 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
416 : TARGET_FUSE_CMP_AND_BRANCH_32)
417 #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
418 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
419 #define TARGET_FUSE_ALU_AND_BRANCH \
420 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
421 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
422 #define TARGET_AVOID_LEA_FOR_ADDR \
423 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
424 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
425 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
426 #define TARGET_AVX256_SPLIT_REGS \
427 ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS]
428 #define TARGET_AVX512_SPLIT_REGS \
429 ix86_tune_features[X86_TUNE_AVX512_SPLIT_REGS]
430 #define TARGET_GENERAL_REGS_SSE_SPILL \
431 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
432 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
433 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
434 #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
435 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
436 #define TARGET_ADJUST_UNROLL \
437 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
438 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \
439 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
440 #define TARGET_ONE_IF_CONV_INSN \
441 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
442 #define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE]
443 #define TARGET_EMIT_VZEROUPPER \
444 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
445 #define TARGET_EXPAND_ABS \
446 ix86_tune_features[X86_TUNE_EXPAND_ABS]
447 #define TARGET_V2DF_REDUCTION_PREFER_HADDPD \
448 ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD]
449 #define TARGET_DEST_FALSE_DEP_FOR_GLC \
450 ix86_tune_features[X86_TUNE_DEST_FALSE_DEP_FOR_GLC]
451
452 /* Feature tests against the various architecture variations. */
453 enum ix86_arch_indices {
454 X86_ARCH_CMOV,
455 X86_ARCH_CMPXCHG,
456 X86_ARCH_CMPXCHG8B,
457 X86_ARCH_XADD,
458 X86_ARCH_BSWAP,
459
460 X86_ARCH_LAST
461 };
462
463 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
464
465 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
466 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
467 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
468 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
469 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
470
471 /* For sane SSE instruction set generation we need fcomi instruction.
472 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
473 expands to a sequence that includes conditional move. */
474 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
475
476 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
477
478 extern unsigned char ix86_prefetch_sse;
479 #define TARGET_PREFETCH_SSE ix86_prefetch_sse
480
481 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
482
483 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
484 #define TARGET_MIX_SSE_I387 \
485 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
486
487 #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
488 #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
489 #define TARGET_HARD_XF_REGS (TARGET_80387)
490
491 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
492 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
493 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
494 #define TARGET_SUN_TLS 0
495
496 #ifndef TARGET_64BIT_DEFAULT
497 #define TARGET_64BIT_DEFAULT 0
498 #endif
499 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
500 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
501 #endif
502
503 #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
504 #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
505
506 /* Fence to use after loop using storent. */
507
508 extern GTY(()) tree x86_mfence;
509 #define FENCE_FOLLOWING_MOVNT x86_mfence
510
511 /* Once GDB has been enhanced to deal with functions without frame
512 pointers, we can change this to allow for elimination of
513 the frame pointer in leaf functions. */
514 #define TARGET_DEFAULT 0
515
516 /* Extra bits to force. */
517 #define TARGET_SUBTARGET_DEFAULT 0
518 #define TARGET_SUBTARGET_ISA_DEFAULT 0
519
520 /* Extra bits to force on w/ 32-bit mode. */
521 #define TARGET_SUBTARGET32_DEFAULT 0
522 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
523
524 /* Extra bits to force on w/ 64-bit mode. */
525 #define TARGET_SUBTARGET64_DEFAULT 0
526 /* Enable MMX, SSE and SSE2 by default. */
527 #define TARGET_SUBTARGET64_ISA_DEFAULT \
528 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
529
530 /* Replace MACH-O, ifdefs by in-line tests, where possible.
531 (a) Macros defined in config/i386/darwin.h */
532 #define TARGET_MACHO 0
533 #define TARGET_MACHO_SYMBOL_STUBS 0
534 #define MACHOPIC_ATT_STUB 0
535 /* (b) Macros defined in config/darwin.h */
536 #define MACHO_DYNAMIC_NO_PIC_P 0
537 #define MACHOPIC_INDIRECT 0
538 #define MACHOPIC_PURE 0
539
540 /* For the RDOS */
541 #define TARGET_RDOS 0
542
543 /* For the Windows 64-bit ABI. */
544 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
545
546 /* For the Windows 32-bit ABI. */
547 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
548
549 /* This is re-defined by cygming.h. */
550 #define TARGET_SEH 0
551
552 /* The default abi used by target. */
553 #define DEFAULT_ABI SYSV_ABI
554
555 /* The default TLS segment register used by target. */
556 #define DEFAULT_TLS_SEG_REG \
557 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
558
559 /* Subtargets may reset this to 1 in order to enable 96-bit long double
560 with the rounding mode forced to 53 bits. */
561 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
562
563 #ifndef SUBTARGET_DRIVER_SELF_SPECS
564 # define SUBTARGET_DRIVER_SELF_SPECS ""
565 #endif
566
567 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS
568
569 /* -march=native handling only makes sense with compiler running on
570 an x86 or x86_64 chip. If changing this condition, also change
571 the condition in driver-i386.cc. */
572 #if defined(__i386__) || defined(__x86_64__)
573 /* In driver-i386.cc. */
574 extern const char *host_detect_local_cpu (int argc, const char **argv);
575 #define EXTRA_SPEC_FUNCTIONS \
576 { "local_cpu_detect", host_detect_local_cpu },
577 #define HAVE_LOCAL_CPU_DETECT
578 #endif
579
580 #if TARGET_64BIT_DEFAULT
581 #define OPT_ARCH64 "!m32"
582 #define OPT_ARCH32 "m32"
583 #else
584 #define OPT_ARCH64 "m64|mx32"
585 #define OPT_ARCH32 "m64|mx32:;"
586 #endif
587
588 /* Support for configure-time defaults of some command line options.
589 The order here is important so that -march doesn't squash the
590 tune or cpu values. */
591 #define OPTION_DEFAULT_SPECS \
592 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
593 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
594 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
595 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
596 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
597 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
598 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
599 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
600 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
601
602 /* Specs for the compiler proper */
603
604 #ifndef CC1_CPU_SPEC
605 #define CC1_CPU_SPEC_1 ""
606
607 #ifndef HAVE_LOCAL_CPU_DETECT
608 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
609 #else
610 #define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}"
611 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
612 "%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \
613 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \
614 %{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}"
615 #endif
616 #endif
617
618 /* Target CPU builtins. */
619 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
620
621 /* Target Pragmas. */
622 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
623
624 #ifndef CC1_SPEC
625 #define CC1_SPEC "%(cc1_cpu) "
626 #endif
627
628 /* This macro defines names of additional specifications to put in the
629 specs that can be used in various specifications like CC1_SPEC. Its
630 definition is an initializer with a subgrouping for each command option.
631
632 Each subgrouping contains a string constant, that defines the
633 specification name, and a string constant that used by the GCC driver
634 program.
635
636 Do not define this macro if it does not need to do anything. */
637
638 #ifndef SUBTARGET_EXTRA_SPECS
639 #define SUBTARGET_EXTRA_SPECS
640 #endif
641
642 #define EXTRA_SPECS \
643 { "cc1_cpu", CC1_CPU_SPEC }, \
644 SUBTARGET_EXTRA_SPECS
645
646
647 /* Whether to allow x87 floating-point arithmetic on MODE (one of
648 SFmode, DFmode and XFmode) in the current excess precision
649 configuration. */
650 #define X87_ENABLE_ARITH(MODE) \
651 (ix86_unsafe_math_optimizations \
652 || ix86_excess_precision == EXCESS_PRECISION_FAST \
653 || (MODE) == XFmode)
654
655 /* Likewise, whether to allow direct conversions from integer mode
656 IMODE (HImode, SImode or DImode) to MODE. */
657 #define X87_ENABLE_FLOAT(MODE, IMODE) \
658 (ix86_unsafe_math_optimizations \
659 || ix86_excess_precision == EXCESS_PRECISION_FAST \
660 || (MODE) == XFmode \
661 || ((MODE) == DFmode && (IMODE) == SImode) \
662 || (IMODE) == HImode)
663
664 /* target machine storage layout */
665
666 #define SHORT_TYPE_SIZE 16
667 #define INT_TYPE_SIZE 32
668 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
669 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
670 #define LONG_LONG_TYPE_SIZE 64
671 #define FLOAT_TYPE_SIZE 32
672 #define DOUBLE_TYPE_SIZE 64
673 #define LONG_DOUBLE_TYPE_SIZE \
674 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
675
676 #define WIDEST_HARDWARE_FP_SIZE 80
677
678 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
679 #define MAX_BITS_PER_WORD 64
680 #else
681 #define MAX_BITS_PER_WORD 32
682 #endif
683
684 /* Define this if most significant byte of a word is the lowest numbered. */
685 /* That is true on the 80386. */
686
687 #define BITS_BIG_ENDIAN 0
688
689 /* Define this if most significant byte of a word is the lowest numbered. */
690 /* That is not true on the 80386. */
691 #define BYTES_BIG_ENDIAN 0
692
693 /* Define this if most significant word of a multiword number is the lowest
694 numbered. */
695 /* Not true for 80386 */
696 #define WORDS_BIG_ENDIAN 0
697
698 /* Width of a word, in units (bytes). */
699 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
700
701 #ifndef IN_LIBGCC2
702 #define MIN_UNITS_PER_WORD 4
703 #endif
704
705 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
706 #define PARM_BOUNDARY BITS_PER_WORD
707
708 /* Boundary (in *bits*) on which stack pointer should be aligned. */
709 #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD)
710
711 /* Stack boundary of the main function guaranteed by OS. */
712 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
713
714 /* Minimum stack boundary. */
715 #define MIN_STACK_BOUNDARY BITS_PER_WORD
716
717 /* Boundary (in *bits*) on which the stack pointer prefers to be
718 aligned; the compiler cannot rely on having this alignment. */
719 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
720
721 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
722 both 32bit and 64bit, to support codes that need 128 bit stack
723 alignment for SSE instructions, but can't realign the stack. */
724 #define PREFERRED_STACK_BOUNDARY_DEFAULT \
725 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
726
727 /* 1 if -mstackrealign should be turned on by default. It will
728 generate an alternate prologue and epilogue that realigns the
729 runtime stack if nessary. This supports mixing codes that keep a
730 4-byte aligned stack, as specified by i386 psABI, with codes that
731 need a 16-byte aligned stack, as required by SSE instructions. */
732 #define STACK_REALIGN_DEFAULT 0
733
734 /* Boundary (in *bits*) on which the incoming stack is aligned. */
735 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
736
737 /* According to Windows x64 software convention, the maximum stack allocatable
738 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
739 instructions allowed to adjust the stack pointer in the epilog, forcing the
740 use of frame pointer for frames larger than 2 GB. This theorical limit
741 is reduced by 256, an over-estimated upper bound for the stack use by the
742 prologue.
743 We define only one threshold for both the prolog and the epilog. When the
744 frame size is larger than this threshold, we allocate the area to save SSE
745 regs, then save them, and then allocate the remaining. There is no SEH
746 unwind info for this later allocation. */
747 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
748
749 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
750 mandatory for the 64-bit ABI, and may or may not be true for other
751 operating systems. */
752 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
753
754 /* Minimum allocation boundary for the code of a function. */
755 #define FUNCTION_BOUNDARY 8
756
757 /* C++ stores the virtual bit in the lowest bit of function pointers. */
758 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
759
760 /* Minimum size in bits of the largest boundary to which any
761 and all fundamental data types supported by the hardware
762 might need to be aligned. No data type wants to be aligned
763 rounder than this.
764
765 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
766 and Pentium Pro XFmode values at 128 bit boundaries.
767
768 When increasing the maximum, also update
769 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
770
771 #define BIGGEST_ALIGNMENT \
772 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)))
773
774 /* Maximum stack alignment. */
775 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
776
777 /* Alignment value for attribute ((aligned)). It is a constant since
778 it is the part of the ABI. We shouldn't change it with -mavx. */
779 #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
780
781 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
782 #define ALIGN_MODE_128(MODE) \
783 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
784
785 /* The published ABIs say that doubles should be aligned on word
786 boundaries, so lower the alignment for structure fields unless
787 -malign-double is set. */
788
789 /* ??? Blah -- this macro is used directly by libobjc. Since it
790 supports no vector modes, cut out the complexity and fall back
791 on BIGGEST_FIELD_ALIGNMENT. */
792 #ifdef IN_TARGET_LIBS
793 #ifdef __x86_64__
794 #define BIGGEST_FIELD_ALIGNMENT 128
795 #else
796 #define BIGGEST_FIELD_ALIGNMENT 32
797 #endif
798 #else
799 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
800 x86_field_alignment ((TYPE), (COMPUTED))
801 #endif
802
803 /* If defined, a C expression to compute the alignment for a static
804 variable. TYPE is the data type, and ALIGN is the alignment that
805 the object would ordinarily have. The value of this macro is used
806 instead of that alignment to align the object.
807
808 If this macro is not defined, then ALIGN is used.
809
810 One use of this macro is to increase alignment of medium-size
811 data to make it all fit in fewer cache lines. Another is to
812 cause character arrays to be word-aligned so that `strcpy' calls
813 that copy constants to character arrays can be done inline. */
814
815 #define DATA_ALIGNMENT(TYPE, ALIGN) \
816 ix86_data_alignment ((TYPE), (ALIGN), true)
817
818 /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
819 some alignment increase, instead of optimization only purposes. E.g.
820 AMD x86-64 psABI says that variables with array type larger than 15 bytes
821 must be aligned to 16 byte boundaries.
822
823 If this macro is not defined, then ALIGN is used. */
824
825 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
826 ix86_data_alignment ((TYPE), (ALIGN), false)
827
828 /* If defined, a C expression to compute the alignment for a local
829 variable. TYPE is the data type, and ALIGN is the alignment that
830 the object would ordinarily have. The value of this macro is used
831 instead of that alignment to align the object.
832
833 If this macro is not defined, then ALIGN is used.
834
835 One use of this macro is to increase alignment of medium-size
836 data to make it all fit in fewer cache lines. */
837
838 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
839 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
840
841 /* If defined, a C expression to compute the alignment for stack slot.
842 TYPE is the data type, MODE is the widest mode available, and ALIGN
843 is the alignment that the slot would ordinarily have. The value of
844 this macro is used instead of that alignment to align the slot.
845
846 If this macro is not defined, then ALIGN is used when TYPE is NULL,
847 Otherwise, LOCAL_ALIGNMENT will be used.
848
849 One use of this macro is to set alignment of stack slot to the
850 maximum alignment of all possible modes which the slot may have. */
851
852 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
853 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
854
855 /* If defined, a C expression to compute the alignment for a local
856 variable DECL.
857
858 If this macro is not defined, then
859 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
860
861 One use of this macro is to increase alignment of medium-size
862 data to make it all fit in fewer cache lines. */
863
864 #define LOCAL_DECL_ALIGNMENT(DECL) \
865 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
866
867 /* If defined, a C expression to compute the minimum required alignment
868 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
869 MODE, assuming normal alignment ALIGN.
870
871 If this macro is not defined, then (ALIGN) will be used. */
872
873 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
874 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
875
876
877 /* Set this nonzero if move instructions will actually fail to work
878 when given unaligned data. */
879 #define STRICT_ALIGNMENT 0
880
881 /* If bit field type is int, don't let it cross an int,
882 and give entire struct the alignment of an int. */
883 /* Required on the 386 since it doesn't have bit-field insns. */
884 #define PCC_BITFIELD_TYPE_MATTERS 1
885
886 /* Standard register usage. */
887
888 /* This processor has special stack-like registers. See reg-stack.cc
889 for details. */
890
891 #define STACK_REGS
892
893 #define IS_STACK_MODE(MODE) \
894 (X87_FLOAT_MODE_P (MODE) \
895 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
896 || TARGET_MIX_SSE_I387))
897
898 /* Number of actual hardware registers.
899 The hardware registers are assigned numbers for the compiler
900 from 0 to just below FIRST_PSEUDO_REGISTER.
901 All registers that the compiler knows about must be given numbers,
902 even those that are not normally considered general registers.
903
904 In the 80386 we give the 8 general purpose registers the numbers 0-7.
905 We number the floating point registers 8-15.
906 Note that registers 0-7 can be accessed as a short or int,
907 while only 0-3 may be used with byte `mov' instructions.
908
909 Reg 16 does not correspond to any hardware register, but instead
910 appears in the RTL as an argument pointer prior to reload, and is
911 eliminated during reloading in favor of either the stack or frame
912 pointer. */
913
914 #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
915
916 /* Number of hardware registers that go into the DWARF-2 unwind info.
917 If not defined, equals FIRST_PSEUDO_REGISTER. */
918
919 #define DWARF_FRAME_REGISTERS 17
920
921 /* 1 for registers that have pervasive standard uses
922 and are not available for the register allocator.
923 On the 80386, the stack pointer is such, as is the arg pointer.
924
925 REX registers are disabled for 32bit targets in
926 TARGET_CONDITIONAL_REGISTER_USAGE. */
927
928 #define FIXED_REGISTERS \
929 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
930 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
931 /*arg,flags,fpsr,frame*/ \
932 1, 1, 1, 1, \
933 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
934 0, 0, 0, 0, 0, 0, 0, 0, \
935 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
936 0, 0, 0, 0, 0, 0, 0, 0, \
937 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
938 0, 0, 0, 0, 0, 0, 0, 0, \
939 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
940 0, 0, 0, 0, 0, 0, 0, 0, \
941 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
942 0, 0, 0, 0, 0, 0, 0, 0, \
943 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
944 0, 0, 0, 0, 0, 0, 0, 0, \
945 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
946 0, 0, 0, 0, 0, 0, 0, 0 }
947
948 /* 1 for registers not available across function calls.
949 These must include the FIXED_REGISTERS and also any
950 registers that can be used without being saved.
951 The latter must include the registers where values are returned
952 and the register where structure-value addresses are passed.
953 Aside from that, you can include as many other registers as you like.
954
955 Value is set to 1 if the register is call used unconditionally.
956 Bit one is set if the register is call used on TARGET_32BIT ABI.
957 Bit two is set if the register is call used on TARGET_64BIT ABI.
958 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
959
960 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
961
962 #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
963 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
964
965 #define CALL_USED_REGISTERS \
966 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
967 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
968 /*arg,flags,fpsr,frame*/ \
969 1, 1, 1, 1, \
970 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
971 1, 1, 1, 1, 1, 1, 6, 6, \
972 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
973 1, 1, 1, 1, 1, 1, 1, 1, \
974 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
975 1, 1, 1, 1, 2, 2, 2, 2, \
976 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
977 6, 6, 6, 6, 6, 6, 6, 6, \
978 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
979 1, 1, 1, 1, 1, 1, 1, 1, \
980 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
981 1, 1, 1, 1, 1, 1, 1, 1, \
982 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
983 1, 1, 1, 1, 1, 1, 1, 1 }
984
985 /* Order in which to allocate registers. Each register must be
986 listed once, even those in FIXED_REGISTERS. List frame pointer
987 late and fixed registers last. Note that, in general, we prefer
988 registers listed in CALL_USED_REGISTERS, keeping the others
989 available for storage of persistent values.
990
991 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
992 so this is just empty initializer for array. */
993
994 #define REG_ALLOC_ORDER \
995 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
996 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
997 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
998 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
999 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
1000
1001 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1002 to be rearranged based on a particular function. When using sse math,
1003 we want to allocate SSE before x87 registers and vice versa. */
1004
1005 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1006
1007
1008 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1009
1010 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1011 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1012 && GENERAL_REGNO_P (REGNO) \
1013 && ((MODE) == XFmode || (MODE) == XCmode))
1014
1015 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1016
1017 #define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE)
1018
1019 #define VALID_AVX256_REG_MODE(MODE) \
1020 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1021 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1022 || (MODE) == V4DFmode || (MODE) == V16HFmode || (MODE) == V16BFmode)
1023
1024 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1025 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1026
1027 #define VALID_AVX512F_SCALAR_MODE(MODE) \
1028 ((MODE) == DImode || (MODE) == DFmode \
1029 || (MODE) == SImode || (MODE) == SFmode \
1030 || (MODE) == HImode || (MODE) == HFmode || (MODE) == BFmode)
1031
1032 #define VALID_AVX512F_REG_MODE(MODE) \
1033 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1034 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1035 || (MODE) == V4TImode || (MODE) == V32HFmode || (MODE) == V32BFmode)
1036
1037 #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1038 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1039
1040 #define VALID_AVX512VL_128_REG_MODE(MODE) \
1041 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1042 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1043 || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \
1044 || (MODE) == V8BFmode || (MODE) == TImode)
1045
1046 #define VALID_AVX512FP16_REG_MODE(MODE) \
1047 ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode)
1048
1049 #define VALID_SSE2_REG_MODE(MODE) \
1050 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1051 || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \
1052 || (MODE) == V8BFmode || (MODE) == V4BFmode || (MODE) == V2BFmode \
1053 || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
1054 || (MODE) == V2DImode || (MODE) == V2QImode \
1055 || (MODE) == DFmode || (MODE) == DImode \
1056 || (MODE) == HFmode || (MODE) == BFmode)
1057
1058 #define VALID_SSE_REG_MODE(MODE) \
1059 ((MODE) == V1TImode || (MODE) == TImode \
1060 || (MODE) == V4SFmode || (MODE) == V4SImode \
1061 || (MODE) == SFmode || (MODE) == SImode \
1062 || (MODE) == TFmode || (MODE) == TDmode)
1063
1064 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1065 ((MODE) == V2SFmode || (MODE) == SFmode)
1066
1067 /* To match ia32 psABI, V4HFmode should be added here. */
1068 #define VALID_MMX_REG_MODE(MODE) \
1069 ((MODE) == V1DImode || (MODE) == DImode \
1070 || (MODE) == V2SImode || (MODE) == SImode \
1071 || (MODE) == V4HImode || (MODE) == V8QImode \
1072 || (MODE) == V4HFmode || (MODE) == V4BFmode)
1073
1074 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1075
1076 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1077
1078 #define VALID_FP_MODE_P(MODE) \
1079 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1080 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)
1081
1082 #define VALID_INT_MODE_P(MODE) \
1083 ((MODE) == QImode || (MODE) == HImode \
1084 || (MODE) == SImode || (MODE) == DImode \
1085 || (MODE) == CQImode || (MODE) == CHImode \
1086 || (MODE) == CSImode || (MODE) == CDImode \
1087 || (MODE) == SDmode || (MODE) == DDmode \
1088 || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \
1089 || (MODE) == V2HImode || (MODE) == V2HFmode || (MODE) == V2BFmode \
1090 || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \
1091 || (TARGET_64BIT \
1092 && ((MODE) == TImode || (MODE) == CTImode \
1093 || (MODE) == TFmode || (MODE) == TCmode \
1094 || (MODE) == V8QImode || (MODE) == V4HImode \
1095 || (MODE) == V2SImode || (MODE) == TDmode)))
1096
1097 /* Return true for modes passed in SSE registers. */
1098 #define SSE_REG_MODE_P(MODE) \
1099 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1100 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1101 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1102 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1103 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1104 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1105 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1106 || (MODE) == V16SFmode \
1107 || (MODE) == V32HFmode || (MODE) == V16HFmode || (MODE) == V8HFmode \
1108 || (MODE) == V32BFmode || (MODE) == V16BFmode || (MODE) == V8BFmode)
1109
1110 #define X87_FLOAT_MODE_P(MODE) \
1111 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1112
1113 #define SSE_FLOAT_MODE_P(MODE) \
1114 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1115
1116 #define SSE_FLOAT_MODE_SSEMATH_OR_HF_P(MODE) \
1117 ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
1118 || (TARGET_AVX512FP16 && (MODE) == HFmode))
1119
1120 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1121 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1122 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1123
1124 #define VALID_BCST_MODE_P(MODE) \
1125 ((MODE) == SFmode || (MODE) == DFmode \
1126 || (MODE) == SImode || (MODE) == DImode \
1127 || (MODE) == HFmode)
1128
1129 /* It is possible to write patterns to move flags; but until someone
1130 does it, */
1131 #define AVOID_CCMODE_COPIES
1132
1133 /* Specify the modes required to caller save a given hard regno.
1134 We do this on i386 to prevent flags from being saved at all.
1135
1136 Kill any attempts to combine saving of modes. */
1137
1138 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1139 (CC_REGNO_P (REGNO) ? VOIDmode \
1140 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1141 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \
1142 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1143 && TARGET_PARTIAL_REG_STALL) \
1144 || MASK_REGNO_P (REGNO)) ? SImode \
1145 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1146 || MASK_REGNO_P (REGNO)) ? SImode \
1147 : (MODE))
1148
1149 /* Specify the registers used for certain standard purposes.
1150 The values of these macros are register numbers. */
1151
1152 /* on the 386 the pc register is %eip, and is not usable as a general
1153 register. The ordinary mov instructions won't work */
1154 /* #define PC_REGNUM */
1155
1156 /* Base register for access to arguments of the function. */
1157 #define ARG_POINTER_REGNUM ARGP_REG
1158
1159 /* Register to use for pushing function arguments. */
1160 #define STACK_POINTER_REGNUM SP_REG
1161
1162 /* Base register for access to local variables of the function. */
1163 #define FRAME_POINTER_REGNUM FRAME_REG
1164 #define HARD_FRAME_POINTER_REGNUM BP_REG
1165
1166 #define FIRST_INT_REG AX_REG
1167 #define LAST_INT_REG SP_REG
1168
1169 #define FIRST_QI_REG AX_REG
1170 #define LAST_QI_REG BX_REG
1171
1172 /* First & last stack-like regs */
1173 #define FIRST_STACK_REG ST0_REG
1174 #define LAST_STACK_REG ST7_REG
1175
1176 #define FIRST_SSE_REG XMM0_REG
1177 #define LAST_SSE_REG XMM7_REG
1178
1179 #define FIRST_MMX_REG MM0_REG
1180 #define LAST_MMX_REG MM7_REG
1181
1182 #define FIRST_REX_INT_REG R8_REG
1183 #define LAST_REX_INT_REG R15_REG
1184
1185 #define FIRST_REX_SSE_REG XMM8_REG
1186 #define LAST_REX_SSE_REG XMM15_REG
1187
1188 #define FIRST_EXT_REX_SSE_REG XMM16_REG
1189 #define LAST_EXT_REX_SSE_REG XMM31_REG
1190
1191 #define FIRST_MASK_REG MASK0_REG
1192 #define LAST_MASK_REG MASK7_REG
1193
1194 /* Override this in other tm.h files to cope with various OS lossage
1195 requiring a frame pointer. */
1196 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1197 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1198 #endif
1199
1200 /* Define the shadow offset for asan. Other OS's can override in the
1201 respective tm.h files. */
1202 #ifndef SUBTARGET_SHADOW_OFFSET
1203 #define SUBTARGET_SHADOW_OFFSET \
1204 (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29)
1205 #endif
1206
1207 /* Make sure we can access arbitrary call frames. */
1208 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1209
1210 /* Register to hold the addressing base for position independent
1211 code access to data items. We don't use PIC pointer for 64bit
1212 mode. Define the regnum to dummy value to prevent gcc from
1213 pessimizing code dealing with EBX.
1214
1215 To avoid clobbering a call-saved register unnecessarily, we renumber
1216 the pic register when possible. The change is visible after the
1217 prologue has been emitted. */
1218
1219 #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1220
1221 #define PIC_OFFSET_TABLE_REGNUM \
1222 (ix86_use_pseudo_pic_reg () \
1223 ? (pic_offset_table_rtx \
1224 ? INVALID_REGNUM \
1225 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1226 : INVALID_REGNUM)
1227
1228 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1229
1230 /* This is overridden by <cygwin.h>. */
1231 #define MS_AGGREGATE_RETURN 0
1232
1233 #define KEEP_AGGREGATE_RETURN_POINTER 0
1234
1235 /* Define the classes of registers for register constraints in the
1236 machine description. Also define ranges of constants.
1237
1238 One of the classes must always be named ALL_REGS and include all hard regs.
1239 If there is more than one class, another class must be named NO_REGS
1240 and contain no registers.
1241
1242 The name GENERAL_REGS must be the name of a class (or an alias for
1243 another name such as ALL_REGS). This is the class of registers
1244 that is allowed by "g" or "r" in a register constraint.
1245 Also, registers outside this class are allocated only when
1246 instructions express preferences for them.
1247
1248 The classes must be numbered in nondecreasing order; that is,
1249 a larger-numbered class must never be contained completely
1250 in a smaller-numbered class. This is why CLOBBERED_REGS class
1251 is listed early, even though in 64-bit mode it contains more
1252 registers than just %eax, %ecx, %edx.
1253
1254 For any two classes, it is very desirable that there be another
1255 class that represents their union.
1256
1257 The flags and fpsr registers are in no class. */
1258
1259 enum reg_class
1260 {
1261 NO_REGS,
1262 AREG, DREG, CREG, BREG, SIREG, DIREG,
1263 AD_REGS, /* %eax/%edx for DImode */
1264 CLOBBERED_REGS, /* call-clobbered integer registers */
1265 Q_REGS, /* %eax %ebx %ecx %edx */
1266 NON_Q_REGS, /* %esi %edi %ebp %esp */
1267 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1268 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1269 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1270 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1271 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1272 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1273 FLOAT_REGS,
1274 SSE_FIRST_REG,
1275 NO_REX_SSE_REGS,
1276 SSE_REGS,
1277 ALL_SSE_REGS,
1278 MMX_REGS,
1279 FLOAT_SSE_REGS,
1280 FLOAT_INT_REGS,
1281 INT_SSE_REGS,
1282 FLOAT_INT_SSE_REGS,
1283 MASK_REGS,
1284 ALL_MASK_REGS,
1285 INT_MASK_REGS,
1286 ALL_REGS,
1287 LIM_REG_CLASSES
1288 };
1289
1290 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1291
1292 #define INTEGER_CLASS_P(CLASS) \
1293 reg_class_subset_p ((CLASS), GENERAL_REGS)
1294 #define FLOAT_CLASS_P(CLASS) \
1295 reg_class_subset_p ((CLASS), FLOAT_REGS)
1296 #define SSE_CLASS_P(CLASS) \
1297 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1298 #define INT_SSE_CLASS_P(CLASS) \
1299 reg_class_subset_p ((CLASS), INT_SSE_REGS)
1300 #define MMX_CLASS_P(CLASS) \
1301 ((CLASS) == MMX_REGS)
1302 #define MASK_CLASS_P(CLASS) \
1303 reg_class_subset_p ((CLASS), ALL_MASK_REGS)
1304 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1305 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1306 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1307 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1308 #define MAYBE_SSE_CLASS_P(CLASS) \
1309 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1310 #define MAYBE_MMX_CLASS_P(CLASS) \
1311 reg_classes_intersect_p ((CLASS), MMX_REGS)
1312 #define MAYBE_MASK_CLASS_P(CLASS) \
1313 reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
1314
1315 #define Q_CLASS_P(CLASS) \
1316 reg_class_subset_p ((CLASS), Q_REGS)
1317
1318 #define MAYBE_NON_Q_CLASS_P(CLASS) \
1319 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1320
1321 /* Give names of register classes as strings for dump file. */
1322
1323 #define REG_CLASS_NAMES \
1324 { "NO_REGS", \
1325 "AREG", "DREG", "CREG", "BREG", \
1326 "SIREG", "DIREG", \
1327 "AD_REGS", \
1328 "CLOBBERED_REGS", \
1329 "Q_REGS", "NON_Q_REGS", \
1330 "TLS_GOTBASE_REGS", \
1331 "INDEX_REGS", \
1332 "LEGACY_REGS", \
1333 "GENERAL_REGS", \
1334 "FP_TOP_REG", "FP_SECOND_REG", \
1335 "FLOAT_REGS", \
1336 "SSE_FIRST_REG", \
1337 "NO_REX_SSE_REGS", \
1338 "SSE_REGS", \
1339 "ALL_SSE_REGS", \
1340 "MMX_REGS", \
1341 "FLOAT_SSE_REGS", \
1342 "FLOAT_INT_REGS", \
1343 "INT_SSE_REGS", \
1344 "FLOAT_INT_SSE_REGS", \
1345 "MASK_REGS", \
1346 "ALL_MASK_REGS", \
1347 "INT_MASK_REGS", \
1348 "ALL_REGS" }
1349
1350 /* Define which registers fit in which classes. This is an initializer
1351 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1352
1353 Note that CLOBBERED_REGS are calculated by
1354 TARGET_CONDITIONAL_REGISTER_USAGE. */
1355
1356 #define REG_CLASS_CONTENTS \
1357 { { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
1358 { 0x01, 0x0, 0x0 }, /* AREG */ \
1359 { 0x02, 0x0, 0x0 }, /* DREG */ \
1360 { 0x04, 0x0, 0x0 }, /* CREG */ \
1361 { 0x08, 0x0, 0x0 }, /* BREG */ \
1362 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1363 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1364 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1365 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1366 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1367 { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
1368 { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1369 { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
1370 { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1371 { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \
1372 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1373 { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1374 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1375 { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1376 { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
1377 { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
1378 { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
1379 { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
1380 { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
1381 { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \
1382 { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \
1383 { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \
1384 { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
1385 { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
1386 { 0x900ff, 0xff0, 0xff0 }, /* INT_MASK_REGS */ \
1387 { 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \
1388 }
1389
1390 /* The same information, inverted:
1391 Return the class number of the smallest class containing
1392 reg number REGNO. This could be a conditional expression
1393 or could index an array. */
1394
1395 #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1396
1397 /* When this hook returns true for MODE, the compiler allows
1398 registers explicitly used in the rtl to be used as spill registers
1399 but prevents the compiler from extending the lifetime of these
1400 registers. */
1401 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1402
1403 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1404 #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1405
1406 #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1407 #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG))
1408
1409 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1410 #define REX_INT_REGNO_P(N) \
1411 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1412
1413 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1414 #define GENERAL_REGNO_P(N) \
1415 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1416
1417 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1418 #define ANY_QI_REGNO_P(N) \
1419 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1420
1421 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1422 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1423
1424 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1425 #define SSE_REGNO_P(N) \
1426 (LEGACY_SSE_REGNO_P (N) \
1427 || REX_SSE_REGNO_P (N) \
1428 || EXT_REX_SSE_REGNO_P (N))
1429
1430 #define LEGACY_SSE_REGNO_P(N) \
1431 IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG)
1432
1433 #define REX_SSE_REGNO_P(N) \
1434 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1435
1436 #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1437
1438 #define EXT_REX_SSE_REGNO_P(N) \
1439 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1440
1441 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1442 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1443
1444 #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1445 #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1446 #define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0)
1447
1448 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1449 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1450
1451 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1452 #define CC_REGNO_P(X) ((X) == FLAGS_REG)
1453
1454 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1455 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1456 || (N) == XMM4_REG \
1457 || (N) == XMM8_REG \
1458 || (N) == XMM12_REG \
1459 || (N) == XMM16_REG \
1460 || (N) == XMM20_REG \
1461 || (N) == XMM24_REG \
1462 || (N) == XMM28_REG)
1463
1464 /* First floating point reg */
1465 #define FIRST_FLOAT_REG FIRST_STACK_REG
1466 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1467
1468 #define GET_SSE_REGNO(N) \
1469 ((N) < 8 ? FIRST_SSE_REG + (N) \
1470 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \
1471 : FIRST_EXT_REX_SSE_REG + (N) - 16)
1472
1473 /* The class value for index registers, and the one for base regs. */
1474
1475 #define INDEX_REG_CLASS INDEX_REGS
1476 #define BASE_REG_CLASS GENERAL_REGS
1477
1478 /* Stack layout; function entry, exit and calling. */
1479
1480 /* Define this if pushing a word on the stack
1481 makes the stack pointer a smaller address. */
1482 #define STACK_GROWS_DOWNWARD 1
1483
1484 /* Define this to nonzero if the nominal address of the stack frame
1485 is at the high-address end of the local variables;
1486 that is, each additional local variable allocated
1487 goes at a more negative offset in the frame. */
1488 #define FRAME_GROWS_DOWNWARD 1
1489
1490 #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES)
1491
1492 /* If defined, the maximum amount of space required for outgoing arguments
1493 will be computed and placed into the variable `crtl->outgoing_args_size'.
1494 No space will be pushed onto the stack for each call; instead, the
1495 function prologue should increase the stack frame size by this amount.
1496
1497 In 32bit mode enabling argument accumulation results in about 5% code size
1498 growth because move instructions are less compact than push. In 64bit
1499 mode the difference is less drastic but visible.
1500
1501 FIXME: Unlike earlier implementations, the size of unwind info seems to
1502 actually grow with accumulation. Is that because accumulated args
1503 unwind info became unnecesarily bloated?
1504
1505 With the 64-bit MS ABI, we can generate correct code with or without
1506 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1507 generated without accumulated args is terrible.
1508
1509 If stack probes are required, the space used for large function
1510 arguments on the stack must also be probed, so enable
1511 -maccumulate-outgoing-args so this happens in the prologue.
1512
1513 We must use argument accumulation in interrupt function if stack
1514 may be realigned to avoid DRAP. */
1515
1516 #define ACCUMULATE_OUTGOING_ARGS \
1517 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1518 && optimize_function_for_speed_p (cfun)) \
1519 || (cfun->machine->func_type != TYPE_NORMAL \
1520 && crtl->stack_realign_needed) \
1521 || TARGET_STACK_PROBE \
1522 || TARGET_64BIT_MS_ABI \
1523 || (TARGET_MACHO && crtl->profile))
1524
1525 /* We want the stack and args grow in opposite directions, even if
1526 targetm.calls.push_argument returns false. */
1527 #define PUSH_ARGS_REVERSED 1
1528
1529 /* Offset of first parameter from the argument pointer register value. */
1530 #define FIRST_PARM_OFFSET(FNDECL) 0
1531
1532 /* Define this macro if functions should assume that stack space has been
1533 allocated for arguments even when their values are passed in registers.
1534
1535 The value of this macro is the size, in bytes, of the area reserved for
1536 arguments passed in registers for the function represented by FNDECL.
1537
1538 This space can be allocated by the caller, or be a part of the
1539 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1540 which. */
1541 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1542
1543 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1544 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1545
1546 /* Define how to find the value returned by a library function
1547 assuming the value has mode MODE. */
1548
1549 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1550
1551 /* Define the size of the result block used for communication between
1552 untyped_call and untyped_return. The block contains a DImode value
1553 followed by the block used by fnsave and frstor. */
1554
1555 #define APPLY_RESULT_SIZE (8+108)
1556
1557 /* 1 if N is a possible register number for function argument passing. */
1558 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1559
1560 /* Define a data type for recording info about an argument list
1561 during the scan of that argument list. This data type should
1562 hold all necessary information about the function itself
1563 and about the args processed so far, enough to enable macros
1564 such as FUNCTION_ARG to determine where the next arg should go. */
1565
1566 typedef struct ix86_args {
1567 int words; /* # words passed so far */
1568 int nregs; /* # registers available for passing */
1569 int regno; /* next available register number */
1570 int fastcall; /* fastcall or thiscall calling convention
1571 is used */
1572 int sse_words; /* # sse words passed so far */
1573 int sse_nregs; /* # sse registers available for passing */
1574 int warn_avx512f; /* True when we want to warn
1575 about AVX512F ABI. */
1576 int warn_avx; /* True when we want to warn about AVX ABI. */
1577 int warn_sse; /* True when we want to warn about SSE ABI. */
1578 int warn_mmx; /* True when we want to warn about MMX ABI. */
1579 int warn_empty; /* True when we want to warn about empty classes
1580 passing ABI change. */
1581 int sse_regno; /* next available sse register number */
1582 int mmx_words; /* # mmx words passed so far */
1583 int mmx_nregs; /* # mmx registers available for passing */
1584 int mmx_regno; /* next available mmx register number */
1585 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1586 int caller; /* true if it is caller. */
1587 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1588 SFmode/DFmode arguments should be passed
1589 in SSE registers. Otherwise 0. */
1590 int stdarg; /* Set to 1 if function is stdarg. */
1591 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1592 MS_ABI for ms abi. */
1593 tree decl; /* Callee decl. */
1594 } CUMULATIVE_ARGS;
1595
1596 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1597 for a call to a function whose data type is FNTYPE.
1598 For a library call, FNTYPE is 0. */
1599
1600 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1601 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1602 (N_NAMED_ARGS) != -1)
1603
1604 /* Output assembler code to FILE to increment profiler label # LABELNO
1605 for profiling a function entry. */
1606
1607 #define FUNCTION_PROFILER(FILE, LABELNO) \
1608 x86_function_profiler ((FILE), (LABELNO))
1609
1610 #define MCOUNT_NAME "_mcount"
1611
1612 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1613
1614 #define PROFILE_COUNT_REGISTER "edx"
1615
1616 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1617 the stack pointer does not matter. The value is tested only in
1618 functions that have frame pointers.
1619 No definition is equivalent to always zero. */
1620 /* Note on the 386 it might be more efficient not to define this since
1621 we have to restore it ourselves from the frame pointer, in order to
1622 use pop */
1623
1624 #define EXIT_IGNORE_STACK 1
1625
1626 /* Define this macro as a C expression that is nonzero for registers
1627 used by the epilogue or the `return' pattern. */
1628
1629 #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1630
1631 /* Output assembler code for a block containing the constant parts
1632 of a trampoline, leaving space for the variable parts. */
1633
1634 /* On the 386, the trampoline contains two instructions:
1635 mov #STATIC,ecx
1636 jmp FUNCTION
1637 The trampoline is generated entirely at runtime. The operand of JMP
1638 is the address of FUNCTION relative to the instruction following the
1639 JMP (which is 5 bytes long). */
1640
1641 /* Length in units of the trampoline for entering a nested function. */
1642
1643 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14)
1644
1645 /* Definitions for register eliminations.
1646
1647 This is an array of structures. Each structure initializes one pair
1648 of eliminable registers. The "from" register number is given first,
1649 followed by "to". Eliminations of the same "from" register are listed
1650 in order of preference.
1651
1652 There are two registers that can always be eliminated on the i386.
1653 The frame pointer and the arg pointer can be replaced by either the
1654 hard frame pointer or to the stack pointer, depending upon the
1655 circumstances. The hard frame pointer is not used before reload and
1656 so it is not eligible for elimination. */
1657
1658 #define ELIMINABLE_REGS \
1659 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1660 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1661 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1662 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1663
1664 /* Define the offset between two registers, one to be eliminated, and the other
1665 its replacement, at the start of a routine. */
1666
1667 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1668 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1669
1670 /* Addressing modes, and classification of registers for them. */
1671
1672 /* Macros to check register numbers against specific register classes. */
1673
1674 /* These assume that REGNO is a hard or pseudo reg number.
1675 They give nonzero only if REGNO is a hard reg of the suitable class
1676 or a pseudo reg currently allocated to a suitable hard reg.
1677 Since they use reg_renumber, they are safe only once reg_renumber
1678 has been allocated, which happens in reginfo.cc during register
1679 allocation. */
1680
1681 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1682 ((REGNO) < STACK_POINTER_REGNUM \
1683 || REX_INT_REGNO_P (REGNO) \
1684 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1685 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1686
1687 #define REGNO_OK_FOR_BASE_P(REGNO) \
1688 (GENERAL_REGNO_P (REGNO) \
1689 || (REGNO) == ARG_POINTER_REGNUM \
1690 || (REGNO) == FRAME_POINTER_REGNUM \
1691 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1692
1693 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1694 and check its validity for a certain class.
1695 We have two alternate definitions for each of them.
1696 The usual definition accepts all pseudo regs; the other rejects
1697 them unless they have been allocated suitable hard regs.
1698 The symbol REG_OK_STRICT causes the latter definition to be used.
1699
1700 Most source files want to accept pseudo regs in the hope that
1701 they will get allocated to the class that the insn wants them to be in.
1702 Source files for reload pass need to be strict.
1703 After reload, it makes no difference, since pseudo regs have
1704 been eliminated by then. */
1705
1706
1707 /* Non strict versions, pseudos are ok. */
1708 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1709 (REGNO (X) < STACK_POINTER_REGNUM \
1710 || REX_INT_REGNO_P (REGNO (X)) \
1711 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1712
1713 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1714 (GENERAL_REGNO_P (REGNO (X)) \
1715 || REGNO (X) == ARG_POINTER_REGNUM \
1716 || REGNO (X) == FRAME_POINTER_REGNUM \
1717 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1718
1719 /* Strict versions, hard registers only */
1720 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1721 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1722
1723 #ifndef REG_OK_STRICT
1724 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1725 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1726
1727 #else
1728 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1729 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1730 #endif
1731
1732 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1733 that is a valid memory address for an instruction.
1734 The MODE argument is the machine mode for the MEM expression
1735 that wants to use this address.
1736
1737 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1738 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1739
1740 See legitimize_pic_address in i386.cc for details as to what
1741 constitutes a legitimate address when -fpic is used. */
1742
1743 #define MAX_REGS_PER_ADDRESS 2
1744
1745 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1746
1747 /* If defined, a C expression to determine the base term of address X.
1748 This macro is used in only one place: `find_base_term' in alias.cc.
1749
1750 It is always safe for this macro to not be defined. It exists so
1751 that alias analysis can understand machine-dependent addresses.
1752
1753 The typical use of this macro is to handle addresses containing
1754 a label_ref or symbol_ref within an UNSPEC. */
1755
1756 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1757
1758 /* Nonzero if the constant value X is a legitimate general operand
1759 when generating PIC code. It is given that flag_pic is on and
1760 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1761
1762 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1763
1764 #define STRIP_UNARY(X) (UNARY_P (X) ? XEXP (X, 0) : X)
1765
1766 #define SYMBOLIC_CONST(X) \
1767 (GET_CODE (X) == SYMBOL_REF \
1768 || GET_CODE (X) == LABEL_REF \
1769 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1770
1771 /* Max number of args passed in registers. If this is more than 3, we will
1772 have problems with ebx (register #4), since it is a caller save register and
1773 is also used as the pic register in ELF. So for now, don't allow more than
1774 3 registers to be passed in registers. */
1775
1776 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1777 #define X86_64_REGPARM_MAX 6
1778 #define X86_64_MS_REGPARM_MAX 4
1779
1780 #define X86_32_REGPARM_MAX 3
1781
1782 #define REGPARM_MAX \
1783 (TARGET_64BIT \
1784 ? (TARGET_64BIT_MS_ABI \
1785 ? X86_64_MS_REGPARM_MAX \
1786 : X86_64_REGPARM_MAX) \
1787 : X86_32_REGPARM_MAX)
1788
1789 #define X86_64_SSE_REGPARM_MAX 8
1790 #define X86_64_MS_SSE_REGPARM_MAX 4
1791
1792 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1793
1794 #define SSE_REGPARM_MAX \
1795 (TARGET_64BIT \
1796 ? (TARGET_64BIT_MS_ABI \
1797 ? X86_64_MS_SSE_REGPARM_MAX \
1798 : X86_64_SSE_REGPARM_MAX) \
1799 : X86_32_SSE_REGPARM_MAX)
1800
1801 #define X86_32_MMX_REGPARM_MAX (TARGET_MMX ? (TARGET_MACHO ? 0 : 3) : 0)
1802
1803 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : X86_32_MMX_REGPARM_MAX)
1804
1805 /* Specify the machine mode that this machine uses
1806 for the index in the tablejump instruction. */
1807 #define CASE_VECTOR_MODE \
1808 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1809
1810 /* Define this as 1 if `char' should by default be signed; else as 0. */
1811 #define DEFAULT_SIGNED_CHAR 1
1812
1813 /* The constant maximum number of bytes that a single instruction can
1814 move quickly between memory and registers or between two memory
1815 locations. */
1816 #define MAX_MOVE_MAX 64
1817
1818 /* Max number of bytes we can move from memory to memory in one
1819 reasonably fast instruction, as opposed to MOVE_MAX_PIECES which
1820 is the number of bytes at a time which we can move efficiently.
1821 MOVE_MAX_PIECES defaults to MOVE_MAX. */
1822
1823 #define MOVE_MAX \
1824 ((TARGET_AVX512F \
1825 && (ix86_move_max == PVW_AVX512 \
1826 || ix86_store_max == PVW_AVX512)) \
1827 ? 64 \
1828 : ((TARGET_AVX \
1829 && (ix86_move_max >= PVW_AVX256 \
1830 || ix86_store_max >= PVW_AVX256)) \
1831 ? 32 \
1832 : ((TARGET_SSE2 \
1833 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1834 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1835 ? 16 : UNITS_PER_WORD)))
1836
1837 /* STORE_MAX_PIECES is the number of bytes at a time that we can store
1838 efficiently. Allow 16/32/64 bytes only if inter-unit move is enabled
1839 since vec_duplicate enabled by inter-unit move is used to implement
1840 store_by_pieces of 16/32/64 bytes. */
1841 #define STORE_MAX_PIECES \
1842 (TARGET_INTER_UNIT_MOVES_TO_VEC \
1843 ? ((TARGET_AVX512F && ix86_store_max == PVW_AVX512) \
1844 ? 64 \
1845 : ((TARGET_AVX \
1846 && ix86_store_max >= PVW_AVX256) \
1847 ? 32 \
1848 : ((TARGET_SSE2 \
1849 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1850 ? 16 : UNITS_PER_WORD))) \
1851 : UNITS_PER_WORD)
1852
1853 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1854 move-instruction pairs, we will do a cpymem or libcall instead.
1855 Increasing the value will always make code faster, but eventually
1856 incurs high cost in increased code size.
1857
1858 If you don't define this, a reasonable default is used. */
1859
1860 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1861
1862 /* If a clear memory operation would take CLEAR_RATIO or more simple
1863 move-instruction sequences, we will do a clrmem or libcall instead. */
1864
1865 #define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2)
1866
1867 /* Define if shifts truncate the shift count which implies one can
1868 omit a sign-extension or zero-extension of a shift count.
1869
1870 On i386, shifts do truncate the count. But bit test instructions
1871 take the modulo of the bit offset operand. */
1872
1873 /* #define SHIFT_COUNT_TRUNCATED */
1874
1875 /* A macro to update M and UNSIGNEDP when an object whose type is
1876 TYPE and which has the specified mode and signedness is to be
1877 stored in a register. This macro is only called when TYPE is a
1878 scalar type.
1879
1880 On i386 it is sometimes useful to promote HImode and QImode
1881 quantities to SImode. The choice depends on target type. */
1882
1883 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1884 do { \
1885 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1886 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1887 (MODE) = SImode; \
1888 } while (0)
1889
1890 /* Specify the machine mode that pointers have.
1891 After generation of rtl, the compiler makes no further distinction
1892 between pointers and any other objects of this machine mode. */
1893 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1894
1895 /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save.
1896 NONLOCAL needs space to save both shadow stack and stack pointers.
1897
1898 FIXME: We only need to save and restore stack pointer in ptr_mode.
1899 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode
1900 to save and restore stack pointer. See
1901 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150
1902 */
1903 #define STACK_SAVEAREA_MODE(LEVEL) \
1904 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode)
1905
1906 /* Specify the machine_mode of the size increment
1907 operand of an 'allocate_stack' named pattern. */
1908 #define STACK_SIZE_MODE Pmode
1909
1910 /* A C expression whose value is zero if pointers that need to be extended
1911 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1912 greater then zero if they are zero-extended and less then zero if the
1913 ptr_extend instruction should be used. */
1914
1915 #define POINTERS_EXTEND_UNSIGNED 1
1916
1917 /* A function address in a call instruction
1918 is a byte address (for indexing purposes)
1919 so give the MEM rtx a byte's mode. */
1920 #define FUNCTION_MODE QImode
1921
1922
1923 /* A C expression for the cost of a branch instruction. A value of 1
1924 is the default; other values are interpreted relative to that. */
1925
1926 #define BRANCH_COST(speed_p, predictable_p) \
1927 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1928
1929 /* An integer expression for the size in bits of the largest integer machine
1930 mode that should actually be used. We allow pairs of registers. */
1931 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1932
1933 /* Define this macro as a C expression which is nonzero if accessing
1934 less than a word of memory (i.e. a `char' or a `short') is no
1935 faster than accessing a word of memory, i.e., if such access
1936 require more than one instruction or if there is no difference in
1937 cost between byte and (aligned) word loads.
1938
1939 When this macro is not defined, the compiler will access a field by
1940 finding the smallest containing object; when it is defined, a
1941 fullword load will be used if alignment permits. Unless bytes
1942 accesses are faster than word accesses, using word accesses is
1943 preferable since it may eliminate subsequent memory access if
1944 subsequent accesses occur to other fields in the same word of the
1945 structure, but to different bytes. */
1946
1947 #define SLOW_BYTE_ACCESS 0
1948
1949 /* Define this macro if it is as good or better to call a constant
1950 function address than to call an address kept in a register.
1951
1952 Desirable on the 386 because a CALL with a constant address is
1953 faster than one with a register address. */
1954
1955 #define NO_FUNCTION_CSE 1
1956
1957 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1958 return the mode to be used for the comparison.
1959
1960 For floating-point equality comparisons, CCFPEQmode should be used.
1961 VOIDmode should be used in all other cases.
1962
1963 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1964 possible, to allow for more combinations. */
1965
1966 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1967
1968 /* Return nonzero if MODE implies a floating point inequality can be
1969 reversed. */
1970
1971 #define REVERSIBLE_CC_MODE(MODE) 1
1972
1973 /* A C expression whose value is reversed condition code of the CODE for
1974 comparison done in CC_MODE mode. */
1975 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1976
1977
1978 /* Control the assembler format that we output, to the extent
1979 this does not vary between assemblers. */
1980
1981 /* How to refer to registers in assembler output.
1982 This sequence is indexed by compiler's hard-register-number (see above). */
1983
1984 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1985 For non floating point regs, the following are the HImode names.
1986
1987 For float regs, the stack top is sometimes referred to as "%st(0)"
1988 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1989 "y" code. */
1990
1991 #define HI_REGISTER_NAMES \
1992 {"ax","dx","cx","bx","si","di","bp","sp", \
1993 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1994 "argp", "flags", "fpsr", "frame", \
1995 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1996 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1997 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1998 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
1999 "xmm16", "xmm17", "xmm18", "xmm19", \
2000 "xmm20", "xmm21", "xmm22", "xmm23", \
2001 "xmm24", "xmm25", "xmm26", "xmm27", \
2002 "xmm28", "xmm29", "xmm30", "xmm31", \
2003 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }
2004
2005 #define REGISTER_NAMES HI_REGISTER_NAMES
2006
2007 #define QI_REGISTER_NAMES \
2008 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"}
2009
2010 #define QI_HIGH_REGISTER_NAMES \
2011 {"ah", "dh", "ch", "bh"}
2012
2013 /* Table of additional register names to use in user input. */
2014
2015 #define ADDITIONAL_REGISTER_NAMES \
2016 { \
2017 { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
2018 { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
2019 { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
2020 { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
2021 { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
2022 { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \
2023 { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
2024 { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
2025 { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
2026 { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
2027 { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
2028 { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
2029 { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
2030 { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
2031 { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
2032 { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
2033 { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
2034 { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
2035 { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
2036 { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
2037 { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
2038 { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
2039 { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
2040 }
2041
2042 /* How to renumber registers for gdb. */
2043
2044 #define DEBUGGER_REGNO(N) \
2045 (TARGET_64BIT ? debugger64_register_map[(N)] : debugger_register_map[(N)])
2046
2047 extern int const debugger_register_map[FIRST_PSEUDO_REGISTER];
2048 extern int const debugger64_register_map[FIRST_PSEUDO_REGISTER];
2049 extern int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER];
2050
2051 /* Before the prologue, RA is at 0(%esp). */
2052 #define INCOMING_RETURN_ADDR_RTX \
2053 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2054
2055 /* After the prologue, RA is at -4(AP) in the current frame. */
2056 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2057 ((COUNT) == 0 \
2058 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2059 -UNITS_PER_WORD)) \
2060 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2061
2062 /* PC is dbx register 8; let's use that column for RA. */
2063 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2064
2065 /* Before the prologue, there are return address and error code for
2066 exception handler on the top of the frame. */
2067 #define INCOMING_FRAME_SP_OFFSET \
2068 (cfun->machine->func_type == TYPE_EXCEPTION \
2069 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2070
2071 /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in
2072 .cfi_startproc. */
2073 #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2074
2075 /* Describe how we implement __builtin_eh_return. */
2076 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2077 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2078
2079
2080 /* Select a format to encode pointers in exception handling data. CODE
2081 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2082 true if the symbol may be affected by dynamic relocations.
2083
2084 ??? All x86 object file formats are capable of representing this.
2085 After all, the relocation needed is the same as for the call insn.
2086 Whether or not a particular assembler allows us to enter such, I
2087 guess we'll have to see. */
2088 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2089 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2090
2091 /* These are a couple of extensions to the formats accepted
2092 by asm_fprintf:
2093 %z prints out opcode suffix for word-mode instruction
2094 %r prints out word-mode name for reg_names[arg] */
2095 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2096 case 'z': \
2097 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2098 break; \
2099 \
2100 case 'r': \
2101 { \
2102 unsigned int regno = va_arg ((ARGS), int); \
2103 if (LEGACY_INT_REGNO_P (regno)) \
2104 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2105 fputs (reg_names[regno], (FILE)); \
2106 break; \
2107 }
2108
2109 /* This is how to output an insn to push a register on the stack. */
2110
2111 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2112 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2113
2114 /* This is how to output an insn to pop a register from the stack. */
2115
2116 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2117 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2118
2119 /* This is how to output an element of a case-vector that is absolute. */
2120
2121 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2122 ix86_output_addr_vec_elt ((FILE), (VALUE))
2123
2124 /* This is how to output an element of a case-vector that is relative. */
2125
2126 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2127 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2128
2129 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2130
2131 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2132 { \
2133 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2134 (PTR) += TARGET_AVX ? 1 : 2; \
2135 }
2136
2137 /* A C statement or statements which output an assembler instruction
2138 opcode to the stdio stream STREAM. The macro-operand PTR is a
2139 variable of type `char *' which points to the opcode name in
2140 its "internal" form--the form that is written in the machine
2141 description. */
2142
2143 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2144 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2145
2146 /* A C statement to output to the stdio stream FILE an assembler
2147 command to pad the location counter to a multiple of 1<<LOG
2148 bytes if it is within MAX_SKIP bytes. */
2149
2150 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2151 # define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2152 do { \
2153 if ((LOG) != 0) { \
2154 if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \
2155 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2156 else \
2157 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2158 } \
2159 } while (0)
2160 #endif
2161
2162 /* Write the extra assembler code needed to declare a function
2163 properly. */
2164
2165 #undef ASM_OUTPUT_FUNCTION_LABEL
2166 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2167 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2168
2169 /* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM.
2170 If not defined, assemble_name will be used to output the name of the
2171 symbol. This macro may be used to modify the way a symbol is referenced
2172 depending on information encoded by TARGET_ENCODE_SECTION_INFO. */
2173
2174 #ifndef ASM_OUTPUT_SYMBOL_REF
2175 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \
2176 do { \
2177 const char *name \
2178 = assemble_name_resolve (XSTR (x, 0)); \
2179 /* In -masm=att wrap identifiers that start with $ \
2180 into parens. */ \
2181 if (ASSEMBLER_DIALECT == ASM_ATT \
2182 && name[0] == '$' \
2183 && user_label_prefix[0] == '\0') \
2184 { \
2185 fputc ('(', (FILE)); \
2186 assemble_name_raw ((FILE), name); \
2187 fputc (')', (FILE)); \
2188 } \
2189 else \
2190 assemble_name_raw ((FILE), name); \
2191 } while (0)
2192 #endif
2193
2194 /* Under some conditions we need jump tables in the text section,
2195 because the assembler cannot handle label differences between
2196 sections. */
2197
2198 #define JUMP_TABLES_IN_TEXT_SECTION \
2199 (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA))
2200
2201 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2202 and switch back. For x86 we do this only to save a few bytes that
2203 would otherwise be unused in the text section. */
2204 #define CRT_MKSTR2(VAL) #VAL
2205 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2206
2207 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2208 asm (SECTION_OP "\n\t" \
2209 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2210 TEXT_SECTION_ASM_OP);
2211
2212 /* Default threshold for putting data in large sections
2213 with x86-64 medium memory model */
2214 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2215
2216 /* Which processor to tune code generation for. These must be in sync
2217 with processor_target_table in i386.cc. */
2218
2219 enum processor_type
2220 {
2221 PROCESSOR_GENERIC = 0,
2222 PROCESSOR_I386, /* 80386 */
2223 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2224 PROCESSOR_PENTIUM,
2225 PROCESSOR_LAKEMONT,
2226 PROCESSOR_PENTIUMPRO,
2227 PROCESSOR_PENTIUM4,
2228 PROCESSOR_NOCONA,
2229 PROCESSOR_CORE2,
2230 PROCESSOR_NEHALEM,
2231 PROCESSOR_SANDYBRIDGE,
2232 PROCESSOR_HASWELL,
2233 PROCESSOR_BONNELL,
2234 PROCESSOR_SILVERMONT,
2235 PROCESSOR_GOLDMONT,
2236 PROCESSOR_GOLDMONT_PLUS,
2237 PROCESSOR_TREMONT,
2238 PROCESSOR_SIERRAFOREST,
2239 PROCESSOR_GRANDRIDGE,
2240 PROCESSOR_KNL,
2241 PROCESSOR_KNM,
2242 PROCESSOR_SKYLAKE,
2243 PROCESSOR_SKYLAKE_AVX512,
2244 PROCESSOR_CANNONLAKE,
2245 PROCESSOR_ICELAKE_CLIENT,
2246 PROCESSOR_ICELAKE_SERVER,
2247 PROCESSOR_CASCADELAKE,
2248 PROCESSOR_TIGERLAKE,
2249 PROCESSOR_COOPERLAKE,
2250 PROCESSOR_SAPPHIRERAPIDS,
2251 PROCESSOR_ALDERLAKE,
2252 PROCESSOR_ROCKETLAKE,
2253 PROCESSOR_GRANITERAPIDS,
2254 PROCESSOR_INTEL,
2255 PROCESSOR_LUJIAZUI,
2256 PROCESSOR_GEODE,
2257 PROCESSOR_K6,
2258 PROCESSOR_ATHLON,
2259 PROCESSOR_K8,
2260 PROCESSOR_AMDFAM10,
2261 PROCESSOR_BDVER1,
2262 PROCESSOR_BDVER2,
2263 PROCESSOR_BDVER3,
2264 PROCESSOR_BDVER4,
2265 PROCESSOR_BTVER1,
2266 PROCESSOR_BTVER2,
2267 PROCESSOR_ZNVER1,
2268 PROCESSOR_ZNVER2,
2269 PROCESSOR_ZNVER3,
2270 PROCESSOR_ZNVER4,
2271 PROCESSOR_max
2272 };
2273
2274 #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
2275 extern const char *const processor_names[];
2276
2277 #include "wide-int-bitmask.h"
2278
2279 enum pta_flag
2280 {
2281 #define DEF_PTA(NAME) _ ## NAME,
2282 #include "i386-isa.def"
2283 #undef DEF_PTA
2284 END_PTA
2285 };
2286
2287 /* wide_int_bitmask can handle only 128 flags. */
2288 STATIC_ASSERT (END_PTA <= 128);
2289
2290 #define WIDE_INT_BITMASK_FROM_NTH(N) (N < 64 ? wide_int_bitmask (0, 1ULL << N) \
2291 : wide_int_bitmask (1ULL << (N - 64), 0))
2292
2293 #define DEF_PTA(NAME) constexpr wide_int_bitmask PTA_ ## NAME \
2294 = WIDE_INT_BITMASK_FROM_NTH ((pta_flag) _ ## NAME);
2295 #include "i386-isa.def"
2296 #undef DEF_PTA
2297
2298 constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE
2299 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR;
2300 constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE
2301 & (~PTA_NO_SAHF))
2302 | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3;
2303 constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2
2304 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2305 | PTA_MOVBE | PTA_XSAVE;
2306 constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3
2307 | PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL;
2308
2309 constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2310 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
2311 constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
2312 | PTA_POPCNT;
2313 constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
2314 constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
2315 | PTA_XSAVEOPT;
2316 constexpr wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
2317 | PTA_RDRND | PTA_F16C;
2318 constexpr wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
2319 | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
2320 constexpr wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
2321 | PTA_PRFCHW;
2322 constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES
2323 | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
2324 constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
2325 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2326 | PTA_CLWB;
2327 constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
2328 | PTA_AVX512VNNI;
2329 constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
2330 constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
2331 | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
2332 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
2333 constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
2334 | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
2335 | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
2336 constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX;
2337 constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
2338 | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
2339 constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
2340 | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL;
2341 constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI
2342 | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG
2343 | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16
2344 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16 | PTA_AVX512BF16;
2345 constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
2346 | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
2347 constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
2348 constexpr wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE
2349 | PTA_RDRND | PTA_PRFCHW;
2350 constexpr wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA
2351 | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT
2352 | PTA_XSAVEOPT | PTA_FSGSBASE;
2353 constexpr wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
2354 | PTA_SGX | PTA_PTWRITE;
2355 constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
2356 | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
2357 constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
2358 | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
2359 | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
2360 | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
2361 constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
2362 | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR;
2363 constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
2364 | PTA_PREFETCHI;
2365 constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
2366 | PTA_AMX_COMPLEX;
2367 constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT;
2368 constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
2369 | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
2370 constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
2371 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2372 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2
2373 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT
2374 | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
2375 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SHA | PTA_LZCNT
2376 | PTA_POPCNT;
2377 constexpr wide_int_bitmask PTA_ZNVER2 = PTA_ZNVER1 | PTA_CLWB | PTA_RDPID
2378 | PTA_WBNOINVD;
2379 constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ
2380 | PTA_PKU;
2381 constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ
2382 | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
2383 | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
2384 | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ;
2385
2386 #ifndef GENERATOR_FILE
2387
2388 #include "insn-attr-common.h"
2389
2390 #include "common/config/i386/i386-cpuinfo.h"
2391
2392 class pta
2393 {
2394 public:
2395 const char *const name; /* processor name or nickname. */
2396 const enum processor_type processor;
2397 const enum attr_cpu schedule;
2398 const wide_int_bitmask flags;
2399 const int model;
2400 const enum feature_priority priority;
2401 };
2402
2403 extern const pta processor_alias_table[];
2404 extern unsigned int const pta_size;
2405 extern unsigned int const num_arch_names;
2406 #endif
2407
2408 #endif
2409
2410 extern enum processor_type ix86_tune;
2411 extern enum processor_type ix86_arch;
2412
2413 /* Size of the RED_ZONE area. */
2414 #define RED_ZONE_SIZE 128
2415 /* Reserved area of the red zone for temporaries. */
2416 #define RED_ZONE_RESERVE 8
2417
2418 extern unsigned int ix86_preferred_stack_boundary;
2419 extern unsigned int ix86_incoming_stack_boundary;
2420
2421 /* Smallest class containing REGNO. */
2422 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2423
2424 enum ix86_fpcmp_strategy {
2425 IX86_FPCMP_SAHF,
2426 IX86_FPCMP_COMI,
2427 IX86_FPCMP_ARITH
2428 };
2429
2430 /* To properly truncate FP values into integers, we need to set i387 control
2431 word. We can't emit proper mode switching code before reload, as spills
2432 generated by reload may truncate values incorrectly, but we still can avoid
2433 redundant computation of new control word by the mode switching pass.
2434 The fldcw instructions are still emitted redundantly, but this is probably
2435 not going to be noticeable problem, as most CPUs do have fast path for
2436 the sequence.
2437
2438 The machinery is to emit simple truncation instructions and split them
2439 before reload to instructions having USEs of two memory locations that
2440 are filled by this code to old and new control word.
2441
2442 Post-reload pass may be later used to eliminate the redundant fildcw if
2443 needed. */
2444
2445 enum ix86_stack_slot
2446 {
2447 SLOT_TEMP = 0,
2448 SLOT_CW_STORED,
2449 SLOT_CW_ROUNDEVEN,
2450 SLOT_CW_TRUNC,
2451 SLOT_CW_FLOOR,
2452 SLOT_CW_CEIL,
2453 SLOT_STV_TEMP,
2454 SLOT_FLOATxFDI_387,
2455 MAX_386_STACK_LOCALS
2456 };
2457
2458 enum ix86_entity
2459 {
2460 X86_DIRFLAG = 0,
2461 AVX_U128,
2462 I387_ROUNDEVEN,
2463 I387_TRUNC,
2464 I387_FLOOR,
2465 I387_CEIL,
2466 MAX_386_ENTITIES
2467 };
2468
2469 enum x86_dirflag_state
2470 {
2471 X86_DIRFLAG_RESET,
2472 X86_DIRFLAG_ANY
2473 };
2474
2475 enum avx_u128_state
2476 {
2477 AVX_U128_CLEAN,
2478 AVX_U128_DIRTY,
2479 AVX_U128_ANY
2480 };
2481
2482 /* Define this macro if the port needs extra instructions inserted
2483 for mode switching in an optimizing compilation. */
2484
2485 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2486 ix86_optimize_mode_switching[(ENTITY)]
2487
2488 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2489 initializer for an array of integers. Each initializer element N
2490 refers to an entity that needs mode switching, and specifies the
2491 number of different modes that might need to be set for this
2492 entity. The position of the initializer in the initializer -
2493 starting counting at zero - determines the integer that is used to
2494 refer to the mode-switched entity in question. */
2495
2496 #define NUM_MODES_FOR_MODE_SWITCHING \
2497 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2498 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2499
2500
2501 /* Avoid renaming of stack registers, as doing so in combination with
2502 scheduling just increases amount of live registers at time and in
2503 the turn amount of fxch instructions needed.
2504
2505 ??? Maybe Pentium chips benefits from renaming, someone can try....
2506
2507 Don't rename evex to non-evex sse registers. */
2508
2509 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2510 (!STACK_REGNO_P (SRC) \
2511 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2512
2513
2514 #define FASTCALL_PREFIX '@'
2515
2516 #ifndef USED_FOR_TARGET
2517 /* Structure describing stack frame layout.
2518 Stack grows downward:
2519
2520 [arguments]
2521 <- ARG_POINTER
2522 saved pc
2523
2524 saved static chain if ix86_static_chain_on_stack
2525
2526 saved frame pointer if frame_pointer_needed
2527 <- HARD_FRAME_POINTER
2528 [saved regs]
2529 <- reg_save_offset
2530 [padding0]
2531 <- stack_realign_offset
2532 [saved SSE regs]
2533 OR
2534 [stub-saved registers for ms x64 --> sysv clobbers
2535 <- Start of out-of-line, stub-saved/restored regs
2536 (see libgcc/config/i386/(sav|res)ms64*.S)
2537 [XMM6-15]
2538 [RSI]
2539 [RDI]
2540 [?RBX] only if RBX is clobbered
2541 [?RBP] only if RBP and RBX are clobbered
2542 [?R12] only if R12 and all previous regs are clobbered
2543 [?R13] only if R13 and all previous regs are clobbered
2544 [?R14] only if R14 and all previous regs are clobbered
2545 [?R15] only if R15 and all previous regs are clobbered
2546 <- end of stub-saved/restored regs
2547 [padding1]
2548 ]
2549 <- sse_reg_save_offset
2550 [padding2]
2551 | <- FRAME_POINTER
2552 [va_arg registers] |
2553 |
2554 [frame] |
2555 |
2556 [padding2] | = to_allocate
2557 <- STACK_POINTER
2558 */
2559 struct GTY(()) ix86_frame
2560 {
2561 int nsseregs;
2562 int nregs;
2563 int va_arg_size;
2564 int red_zone_size;
2565 int outgoing_arguments_size;
2566
2567 /* The offsets relative to ARG_POINTER. */
2568 HOST_WIDE_INT frame_pointer_offset;
2569 HOST_WIDE_INT hard_frame_pointer_offset;
2570 HOST_WIDE_INT stack_pointer_offset;
2571 HOST_WIDE_INT hfp_save_offset;
2572 HOST_WIDE_INT reg_save_offset;
2573 HOST_WIDE_INT stack_realign_allocate;
2574 HOST_WIDE_INT stack_realign_offset;
2575 HOST_WIDE_INT sse_reg_save_offset;
2576
2577 /* When save_regs_using_mov is set, emit prologue using
2578 move instead of push instructions. */
2579 bool save_regs_using_mov;
2580
2581 /* Assume without checking that:
2582 EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */
2583 bool expensive_p;
2584 int expensive_count;
2585 };
2586
2587 /* Machine specific frame tracking during prologue/epilogue generation. All
2588 values are positive, but since the x86 stack grows downward, are subtratced
2589 from the CFA to produce a valid address. */
2590
2591 struct GTY(()) machine_frame_state
2592 {
2593 /* This pair tracks the currently active CFA as reg+offset. When reg
2594 is drap_reg, we don't bother trying to record here the real CFA when
2595 it might really be a DW_CFA_def_cfa_expression. */
2596 rtx cfa_reg;
2597 HOST_WIDE_INT cfa_offset;
2598
2599 /* The current offset (canonically from the CFA) of ESP and EBP.
2600 When stack frame re-alignment is active, these may not be relative
2601 to the CFA. However, in all cases they are relative to the offsets
2602 of the saved registers stored in ix86_frame. */
2603 HOST_WIDE_INT sp_offset;
2604 HOST_WIDE_INT fp_offset;
2605
2606 /* The size of the red-zone that may be assumed for the purposes of
2607 eliding register restore notes in the epilogue. This may be zero
2608 if no red-zone is in effect, or may be reduced from the real
2609 red-zone value by a maximum runtime stack re-alignment value. */
2610 int red_zone_offset;
2611
2612 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2613 value within the frame. If false then the offset above should be
2614 ignored. Note that DRAP, if valid, *always* points to the CFA and
2615 thus has an offset of zero. */
2616 BOOL_BITFIELD sp_valid : 1;
2617 BOOL_BITFIELD fp_valid : 1;
2618 BOOL_BITFIELD drap_valid : 1;
2619
2620 /* Indicate whether the local stack frame has been re-aligned. When
2621 set, the SP/FP offsets above are relative to the aligned frame
2622 and not the CFA. */
2623 BOOL_BITFIELD realigned : 1;
2624
2625 /* Indicates whether the stack pointer has been re-aligned. When set,
2626 SP/FP continue to be relative to the CFA, but the stack pointer
2627 should only be used for offsets > sp_realigned_offset, while
2628 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2629 The flags realigned and sp_realigned are mutually exclusive. */
2630 BOOL_BITFIELD sp_realigned : 1;
2631
2632 /* If sp_realigned is set, this is the last valid offset from the CFA
2633 that can be used for access with the frame pointer. */
2634 HOST_WIDE_INT sp_realigned_fp_last;
2635
2636 /* If sp_realigned is set, this is the offset from the CFA that the stack
2637 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2638 Access via the stack pointer is only valid for offsets that are greater than
2639 this value. */
2640 HOST_WIDE_INT sp_realigned_offset;
2641 };
2642
2643 /* Private to winnt.cc. */
2644 struct seh_frame_state;
2645
2646 enum function_type
2647 {
2648 TYPE_UNKNOWN = 0,
2649 TYPE_NORMAL,
2650 /* The current function is an interrupt service routine with a
2651 pointer argument as specified by the "interrupt" attribute. */
2652 TYPE_INTERRUPT,
2653 /* The current function is an interrupt service routine with a
2654 pointer argument and an integer argument as specified by the
2655 "interrupt" attribute. */
2656 TYPE_EXCEPTION
2657 };
2658
2659 enum queued_insn_type
2660 {
2661 TYPE_NONE = 0,
2662 TYPE_ENDBR,
2663 TYPE_PATCHABLE_AREA
2664 };
2665
2666 struct GTY(()) machine_function {
2667 struct stack_local_entry *stack_locals;
2668 int varargs_gpr_size;
2669 int varargs_fpr_size;
2670 int optimize_mode_switching[MAX_386_ENTITIES];
2671
2672 /* Cached initial frame layout for the current function. */
2673 struct ix86_frame frame;
2674
2675 /* For -fsplit-stack support: A stack local which holds a pointer to
2676 the stack arguments for a function with a variable number of
2677 arguments. This is set at the start of the function and is used
2678 to initialize the overflow_arg_area field of the va_list
2679 structure. */
2680 rtx split_stack_varargs_pointer;
2681
2682 /* This value is used for amd64 targets and specifies the current abi
2683 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2684 ENUM_BITFIELD(calling_abi) call_abi : 8;
2685
2686 /* Nonzero if the function accesses a previous frame. */
2687 BOOL_BITFIELD accesses_prev_frame : 1;
2688
2689 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2690 expander to determine the style used. */
2691 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2692
2693 /* Nonzero if the current function calls pc thunk and
2694 must not use the red zone. */
2695 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2696
2697 /* If true, the current function needs the default PIC register, not
2698 an alternate register (on x86) and must not use the red zone (on
2699 x86_64), even if it's a leaf function. We don't want the
2700 function to be regarded as non-leaf because TLS calls need not
2701 affect register allocation. This flag is set when a TLS call
2702 instruction is expanded within a function, and never reset, even
2703 if all such instructions are optimized away. Use the
2704 ix86_current_function_calls_tls_descriptor macro for a better
2705 approximation. */
2706 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2707
2708 /* If true, the current function has a STATIC_CHAIN is placed on the
2709 stack below the return address. */
2710 BOOL_BITFIELD static_chain_on_stack : 1;
2711
2712 /* If true, it is safe to not save/restore DRAP register. */
2713 BOOL_BITFIELD no_drap_save_restore : 1;
2714
2715 /* Function type. */
2716 ENUM_BITFIELD(function_type) func_type : 2;
2717
2718 /* How to generate indirec branch. */
2719 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
2720
2721 /* If true, the current function has local indirect jumps, like
2722 "indirect_jump" or "tablejump". */
2723 BOOL_BITFIELD has_local_indirect_jump : 1;
2724
2725 /* How to generate function return. */
2726 ENUM_BITFIELD(indirect_branch) function_return_type : 3;
2727
2728 /* If true, the current function is a function specified with
2729 the "interrupt" or "no_caller_saved_registers" attribute. */
2730 BOOL_BITFIELD no_caller_saved_registers : 1;
2731
2732 /* If true, there is register available for argument passing. This
2733 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2734 if there is scratch register available for indirect sibcall. In
2735 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2736 pass arguments and can be used for indirect sibcall. */
2737 BOOL_BITFIELD arg_reg_available : 1;
2738
2739 /* If true, we're out-of-lining reg save/restore for regs clobbered
2740 by 64-bit ms_abi functions calling a sysv_abi function. */
2741 BOOL_BITFIELD call_ms2sysv : 1;
2742
2743 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2744 needs padding prior to out-of-line stub save/restore area. */
2745 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2746
2747 /* This is the number of extra registers saved by stub (valid range is
2748 0-6). Each additional register is only saved/restored by the stubs
2749 if all successive ones are. (Will always be zero when using a hard
2750 frame pointer.) */
2751 unsigned int call_ms2sysv_extra_regs:3;
2752
2753 /* Nonzero if the function places outgoing arguments on stack. */
2754 BOOL_BITFIELD outgoing_args_on_stack : 1;
2755
2756 /* If true, ENDBR or patchable area is queued at function entrance. */
2757 ENUM_BITFIELD(queued_insn_type) insn_queued_at_entrance : 2;
2758
2759 /* If true, the function label has been emitted. */
2760 BOOL_BITFIELD function_label_emitted : 1;
2761
2762 /* True if the function needs a stack frame. */
2763 BOOL_BITFIELD stack_frame_required : 1;
2764
2765 /* True if we should act silently, rather than raise an error for
2766 invalid calls. */
2767 BOOL_BITFIELD silent_p : 1;
2768
2769 /* True if red zone is used. */
2770 BOOL_BITFIELD red_zone_used : 1;
2771
2772 /* The largest alignment, in bytes, of stack slot actually used. */
2773 unsigned int max_used_stack_alignment;
2774
2775 /* During prologue/epilogue generation, the current frame state.
2776 Otherwise, the frame state at the end of the prologue. */
2777 struct machine_frame_state fs;
2778
2779 /* During SEH output, this is non-null. */
2780 struct seh_frame_state * GTY((skip(""))) seh;
2781 };
2782
2783 extern GTY(()) tree sysv_va_list_type_node;
2784 extern GTY(()) tree ms_va_list_type_node;
2785 #endif
2786
2787 #define ix86_stack_locals (cfun->machine->stack_locals)
2788 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2789 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2790 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2791 #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2792 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2793 (cfun->machine->tls_descriptor_call_expanded_p)
2794 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2795 calls are optimized away, we try to detect cases in which it was
2796 optimized away. Since such instructions (use (reg REG_SP)), we can
2797 verify whether there's any such instruction live by testing that
2798 REG_SP is live. */
2799 #define ix86_current_function_calls_tls_descriptor \
2800 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2801 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2802 #define ix86_red_zone_used (cfun->machine->red_zone_used)
2803
2804 /* Control behavior of x86_file_start. */
2805 #define X86_FILE_START_VERSION_DIRECTIVE false
2806 #define X86_FILE_START_FLTUSED false
2807
2808 /* Flag to mark data that is in the large address area. */
2809 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2810 #define SYMBOL_REF_FAR_ADDR_P(X) \
2811 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2812
2813 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2814 have defined always, to avoid ifdefing. */
2815 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2816 #define SYMBOL_REF_DLLIMPORT_P(X) \
2817 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2818
2819 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2820 #define SYMBOL_REF_DLLEXPORT_P(X) \
2821 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2822
2823 #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2824 #define SYMBOL_REF_STUBVAR_P(X) \
2825 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2826
2827 extern void debug_ready_dispatch (void);
2828 extern void debug_dispatch_window (int);
2829
2830 /* The value at zero is only defined for the BMI instructions
2831 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2832 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2833 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 2 : 0)
2834 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2835 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 2 : 0)
2836
2837
2838 /* Flags returned by ix86_get_callcvt (). */
2839 #define IX86_CALLCVT_CDECL 0x1
2840 #define IX86_CALLCVT_STDCALL 0x2
2841 #define IX86_CALLCVT_FASTCALL 0x4
2842 #define IX86_CALLCVT_THISCALL 0x8
2843 #define IX86_CALLCVT_REGPARM 0x10
2844 #define IX86_CALLCVT_SSEREGPARM 0x20
2845
2846 #define IX86_BASE_CALLCVT(FLAGS) \
2847 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2848 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2849
2850 #define RECIP_MASK_NONE 0x00
2851 #define RECIP_MASK_DIV 0x01
2852 #define RECIP_MASK_SQRT 0x02
2853 #define RECIP_MASK_VEC_DIV 0x04
2854 #define RECIP_MASK_VEC_SQRT 0x08
2855 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2856 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2857 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2858
2859 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2860 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2861 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2862 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2863
2864 /* Use 128-bit AVX instructions in the auto-vectorizer. */
2865 #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2866 /* Use 256-bit AVX instructions in the auto-vectorizer. */
2867 #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2868 || prefer_vector_width_type == PVW_AVX256)
2869
2870 #define TARGET_INDIRECT_BRANCH_REGISTER \
2871 (ix86_indirect_branch_register \
2872 || cfun->machine->indirect_branch_type != indirect_branch_keep)
2873
2874 #define IX86_HLE_ACQUIRE (1 << 16)
2875 #define IX86_HLE_RELEASE (1 << 17)
2876
2877 /* For switching between functions with different target attributes. */
2878 #define SWITCHABLE_TARGET 1
2879
2880 #define TARGET_SUPPORTS_WIDE_INT 1
2881
2882 #if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2)
2883 extern enum attr_cpu ix86_schedule;
2884
2885 #define NUM_X86_64_MS_CLOBBERED_REGS 12
2886 #endif
2887
2888 /* __builtin_eh_return can't handle stack realignment, so disable MMX/SSE
2889 in 32-bit libgcc functions that call it. */
2890 #ifndef __x86_64__
2891 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((target ("no-mmx,no-sse")))
2892 #endif
2893
2894 /*
2895 Local variables:
2896 version-control: t
2897 End:
2898 */