1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991-2023 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
23
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
27 <http://www.gnu.org/licenses/>. */
28
29 #ifndef GCC_ARM_H
30 #define GCC_ARM_H
31
32 /* We can't use machine_mode inside a generator file because it
33 hasn't been created yet; we shouldn't be using any code that
34 needs the real definition though, so this ought to be safe. */
35 #ifdef GENERATOR_FILE
36 #define MACHMODE int
37 #else
38 #include "insn-modes.h"
39 #define MACHMODE machine_mode
40 #endif
41
42 #include "config/vxworks-dummy.h"
43
44 /* The architecture define. */
45 extern char arm_arch_name[];
46
47 /* Target CPU builtins. */
48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile)
49
50 #include "config/arm/arm-opts.h"
51
52 /* The processor for which instructions should be scheduled. */
53 extern enum processor_type arm_tune;
54
55 typedef enum arm_cond_code
56 {
57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
59 }
60 arm_cc;
61
62 extern arm_cc arm_current_cc;
63
64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
65
66 /* The maximum number of instructions that is beneficial to
67 conditionally execute. */
68 #undef MAX_CONDITIONAL_EXECUTE
69 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
70
71 extern int arm_target_label;
72 extern int arm_ccfsm_state;
73 extern GTY(()) rtx arm_target_insn;
74 /* Callback to output language specific object attributes. */
75 extern void (*arm_lang_output_object_attributes_hook)(void);
76
77 /* This type is the user-visible __fp16. We need it in a few places in
78 the backend. Defined in arm-builtins.cc. */
79 extern tree arm_fp16_type_node;
80
81 /* This type is the user-visible __bf16. We need it in a few places in
82 the backend. Defined in arm-builtins.cc. */
83 extern tree arm_bf16_type_node;
84 extern tree arm_bf16_ptr_type_node;
85
86
87 #undef CPP_SPEC
88 #define CPP_SPEC "%(subtarget_cpp_spec)"
89
90 #ifndef CC1_SPEC
91 #define CC1_SPEC ""
92 #endif
93
94 /* This macro defines names of additional specifications to put in the specs
95 that can be used in various specifications like CC1_SPEC. Its definition
96 is an initializer with a subgrouping for each command option.
97
98 Each subgrouping contains a string constant, that defines the
99 specification name, and a string constant that used by the GCC driver
100 program.
101
102 Do not define this macro if it does not need to do anything. */
103 #define EXTRA_SPECS \
104 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
105 { "asm_cpu_spec", ASM_CPU_SPEC }, \
106 SUBTARGET_EXTRA_SPECS
107
108 #ifndef SUBTARGET_EXTRA_SPECS
109 #define SUBTARGET_EXTRA_SPECS
110 #endif
111
112 #ifndef SUBTARGET_CPP_SPEC
113 #define SUBTARGET_CPP_SPEC ""
114 #endif
115
116 /* Tree Target Specification. */
117 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags))
118 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2)
119 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2)
120 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags))
121
122 /* Run-time Target Specification. */
123 /* Use hardware floating point instructions. -mgeneral-regs-only prevents
124 the use of floating point instructions and registers but does not prevent
125 emission of floating point pcs attributes. */
126 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \
127 && bitmap_bit_p (arm_active_target.isa, \
128 isa_bit_vfpv2) \
129 && TARGET_32BIT)
130
131 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \
132 && !TARGET_GENERAL_REGS_ONLY)
133
134 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB)
135 /* User has permitted use of FP instructions, if they exist for this
136 target. */
137 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
138 /* Use hardware floating point calling convention. */
139 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
140 #define TARGET_IWMMXT (arm_arch_iwmmxt)
141 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
142 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \
143 && !TARGET_GENERAL_REGS_ONLY)
144 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \
145 && !TARGET_GENERAL_REGS_ONLY)
146 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
147 #define TARGET_ARM (! TARGET_THUMB)
148 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
149 #define TARGET_BACKTRACE (crtl->is_leaf \
150 ? TARGET_TPCS_LEAF_FRAME \
151 : TARGET_TPCS_FRAME)
152 #define TARGET_AAPCS_BASED \
153 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
154
155 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
156 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
157 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
158
159 /* Only 16-bit thumb code. */
160 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
161 /* Arm or Thumb-2 32-bit code. */
162 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
163 /* 32-bit Thumb-2 code. */
164 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
165 /* Thumb-1 only. */
166 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
167
168 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \
169 && !TARGET_THUMB1)
170
171 #define TARGET_CRC32 (arm_arch_crc)
172
173 /* Thumb-2 but also has some conditional arithmetic instructions like csinc,
174 csinv, etc. */
175 #define TARGET_COND_ARITH (arm_arch8_1m_main)
176
177 /* The following two macros concern the ability to execute coprocessor
178 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
179 only ever tested when we know we are generating for VFP hardware; we need
180 to be more careful with TARGET_NEON as noted below. */
181
182 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
183 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32))
184
185 /* FPU supports VFPv3 instructions. */
186 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3))
187
188 /* FPU supports FPv5 instructions. */
189 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5))
190
191 /* FPU only supports VFP single-precision instructions. */
192 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE)
193
194 /* FPU supports VFP double-precision instructions. */
195 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl))
196
197 /* FPU supports half-precision floating-point with NEON element load/store. */
198 #define TARGET_NEON_FP16 \
199 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \
200 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
201
202 /* FPU supports VFP half-precision floating-point conversions. */
203 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
204
205 /* FPU supports converting between HFmode and DFmode in a single hardware
206 step. */
207 #define TARGET_FP16_TO_DOUBLE \
208 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE)
209
210 /* FPU supports fused-multiply-add operations. */
211 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4))
212
213 /* FPU supports Crypto extensions. */
214 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))
215
216 /* FPU supports Neon instructions. The setting of this macro gets
217 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
218 and TARGET_HARD_FLOAT to ensure that NEON instructions are
219 available. */
220 #define TARGET_NEON \
221 (TARGET_32BIT && TARGET_HARD_FLOAT \
222 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
223
224 /* FPU supports ARMv8.1 Adv.SIMD extensions. */
225 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
226
227 /* Supports the Dot Product AdvSIMD extensions. */
228 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \
229 && bitmap_bit_p (arm_active_target.isa, \
230 isa_bit_dotprod) \
231 && arm_arch8_2)
232
233 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */
234 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3)
235
236 /* FPU supports the floating point FP16 instructions for ARMv8.2-A
237 and later. */
238 #define TARGET_VFP_FP16INST \
239 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)
240
241 /* Target supports the floating point FP16 instructions from ARMv8.2-A
242 and later. */
243 #define TARGET_FP16FML (TARGET_NEON \
244 && bitmap_bit_p (arm_active_target.isa, \
245 isa_bit_fp16fml) \
246 && arm_arch8_2)
247
248 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */
249 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
250
251 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */
252 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm)
253
254 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */
255 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \
256 && arm_arch8_2 && arm_arch_bf16)
257 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \
258 && arm_arch8_2 && arm_arch_bf16)
259
260 /* Q-bit is present. */
261 #define TARGET_ARM_QBIT \
262 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7))
263 /* Saturation operation, e.g. SSAT. */
264 #define TARGET_ARM_SAT \
265 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
266 /* "DSP" multiply instructions, eg. SMULxy. */
267 #define TARGET_DSP_MULTIPLY \
268 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em))
269 /* Integer SIMD instructions, and extend-accumulate instructions. */
270 #define TARGET_INT_SIMD \
271 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
272
273 /* Should MOVW/MOVT be used in preference to a constant pool. */
274 #define TARGET_USE_MOVT \
275 (TARGET_HAVE_MOVT \
276 && (arm_disable_literal_pool \
277 || (!optimize_size && !current_tune->prefer_constant_pool)))
278
279 /* Nonzero if this chip provides the DMB instruction. */
280 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
281
282 /* Nonzero if this chip implements a memory barrier via CP15. */
283 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
284 && ! TARGET_THUMB1)
285
286 /* Nonzero if this chip implements a memory barrier instruction. */
287 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
288
289 /* Nonzero if this chip supports ldrex and strex */
290 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \
291 || arm_arch7 \
292 || (arm_arch8 && !arm_arch_notm))
293
294 /* Nonzero if this chip supports LPAE. */
295 #define TARGET_HAVE_LPAE (arm_arch_lpae)
296
297 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
298 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \
299 || arm_arch7 \
300 || (arm_arch8 && !arm_arch_notm))
301
302 /* Nonzero if this chip supports ldrexd and strexd. */
303 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
304 || arm_arch7) && arm_arch_notm)
305
306 /* Nonzero if this chip supports load-acquire and store-release. */
307 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
308
309 /* Nonzero if this chip supports LDAEXD and STLEXD. */
310 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \
311 && TARGET_32BIT \
312 && arm_arch_notm)
313
314 /* Nonzero if this chip provides the MOVW and MOVT instructions. */
315 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
316
317 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */
318 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8)
319
320 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions
321 instructions (most are floating-point related). */
322 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main)
323
324 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \
325 && bitmap_bit_p (arm_active_target.isa, \
326 isa_bit_mve) \
327 && !TARGET_GENERAL_REGS_ONLY)
328
329 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \
330 && bitmap_bit_p (arm_active_target.isa, \
331 isa_bit_mve_float) \
332 && !TARGET_GENERAL_REGS_ONLY)
333
334 /* Non-zero if this target supports Armv8.1-M Mainline pointer-signing
335 extension. */
336 #define TARGET_HAVE_PACBTI (arm_arch8_1m_main \
337 && bitmap_bit_p (arm_active_target.isa, \
338 isa_bit_pacbti))
339
340 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM
341 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few
342 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All
343 the VFP instructions, RTL patterns and register are guarded by
344 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers
345 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE
346 hereafter. */
347
348 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \
349 && bitmap_bit_p (arm_active_target.isa, \
350 isa_bit_vfp_base) \
351 && !TARGET_GENERAL_REGS_ONLY)
352
353 /* Nonzero if integer division instructions supported. */
354 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
355 || (TARGET_THUMB && arm_arch_thumb_hwdiv))
356
357 /* Nonzero if disallow volatile memory access in IT block. */
358 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce)
359
360 /* Nonzero if chip supports the Custom Datapath Extension. */
361 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm)
362
363 /* Should constant I be slplit for OP. */
364 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \
365 ((optimize >= 2) \
366 && can_create_pseudo_p () \
367 && !const_ok_for_op (i, op))
368
369 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
370 then TARGET_AAPCS_BASED must be true -- but the converse does not
371 hold. TARGET_BPABI implies the use of the BPABI runtime library,
372 etc., in addition to just the AAPCS calling conventions. */
373 #ifndef TARGET_BPABI
374 #define TARGET_BPABI false
375 #endif
376
377 /* Transform lane numbers on big endian targets. This is used to allow for the
378 endianness difference between NEON architectural lane numbers and those
379 used in RTL */
380 #define NEON_ENDIAN_LANE_N(mode, n) \
381 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
382
383 /* Support for a compile-time default CPU, et cetera. The rules are:
384 --with-arch is ignored if -march or -mcpu are specified.
385 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
386 by --with-arch.
387 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
388 by -march).
389 --with-float is ignored if -mfloat-abi is specified.
390 --with-fpu is ignored if -mfpu is specified.
391 --with-abi is ignored if -mabi is specified.
392 --with-tls is ignored if -mtls-dialect is specified.
393 Note: --with-mode is not handled here, that has a special rule
394 TARGET_MODE_CHECK that also takes into account the selected CPU and
395 architecture. */
396 #define OPTION_DEFAULT_SPECS \
397 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
398 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
399 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
400 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
401 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
402 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
403 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
404
405 extern const struct arm_fpu_desc
406 {
407 const char *name;
408 enum isa_feature isa_bits[isa_num_bits];
409 } all_fpus[];
410
411 /* Which floating point hardware to schedule for. */
412 extern int arm_fpu_attr;
413
414 #ifndef TARGET_DEFAULT_FLOAT_ABI
415 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
416 #endif
417
418 #ifndef ARM_DEFAULT_ABI
419 #define ARM_DEFAULT_ABI ARM_ABI_APCS
420 #endif
421
422 /* AAPCS based ABIs use short enums by default. */
423 #ifndef ARM_DEFAULT_SHORT_ENUMS
424 #define ARM_DEFAULT_SHORT_ENUMS \
425 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX)
426 #endif
427
428 /* Map each of the micro-architecture variants to their corresponding
429 major architecture revision. */
430
431 enum base_architecture
432 {
433 BASE_ARCH_0 = 0,
434 BASE_ARCH_2 = 2,
435 BASE_ARCH_3 = 3,
436 BASE_ARCH_3M = 3,
437 BASE_ARCH_4 = 4,
438 BASE_ARCH_4T = 4,
439 BASE_ARCH_5T = 5,
440 BASE_ARCH_5TE = 5,
441 BASE_ARCH_5TEJ = 5,
442 BASE_ARCH_6 = 6,
443 BASE_ARCH_6J = 6,
444 BASE_ARCH_6KZ = 6,
445 BASE_ARCH_6K = 6,
446 BASE_ARCH_6T2 = 6,
447 BASE_ARCH_6M = 6,
448 BASE_ARCH_6Z = 6,
449 BASE_ARCH_7 = 7,
450 BASE_ARCH_7A = 7,
451 BASE_ARCH_7R = 7,
452 BASE_ARCH_7M = 7,
453 BASE_ARCH_7EM = 7,
454 BASE_ARCH_8A = 8,
455 BASE_ARCH_8M_BASE = 8,
456 BASE_ARCH_8M_MAIN = 8,
457 BASE_ARCH_8R = 8,
458 BASE_ARCH_9A = 9
459 };
460
461 /* The major revision number of the ARM Architecture implemented by the target. */
462 extern enum base_architecture arm_base_arch;
463
464 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
465 extern int arm_arch4;
466
467 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
468 extern int arm_arch4t;
469
470 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */
471 extern int arm_arch5t;
472
473 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */
474 extern int arm_arch5te;
475
476 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
477 extern int arm_arch6;
478
479 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
480 extern int arm_arch6k;
481
482 /* Nonzero if instructions present in ARMv6-M can be used. */
483 extern int arm_arch6m;
484
485 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
486 extern int arm_arch7;
487
488 /* Nonzero if instructions not present in the 'M' profile can be used. */
489 extern int arm_arch_notm;
490
491 /* Nonzero if instructions present in ARMv7E-M can be used. */
492 extern int arm_arch7em;
493
494 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
495 extern int arm_arch8;
496
497 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */
498 extern int arm_arch8_1;
499
500 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */
501 extern int arm_arch8_2;
502
503 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */
504 extern int arm_arch8_3;
505
506 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
507 extern int arm_arch8_4;
508
509 /* Nonzero if this chip supports the ARM Architecture 8-M Mainline
510 extensions. */
511 extern int arm_arch8m_main;
512
513 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
514 extensions. */
515 extern int arm_arch8_1m_main;
516
517 /* Nonzero if this chip supports the FP16 instructions extension of ARM
518 Architecture 8.2. */
519 extern int arm_fp16_inst;
520
521 /* Nonzero if this chip can benefit from load scheduling. */
522 extern int arm_ld_sched;
523
524 /* Nonzero if this chip is a StrongARM. */
525 extern int arm_tune_strongarm;
526
527 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
528 extern int arm_arch_iwmmxt;
529
530 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
531 extern int arm_arch_iwmmxt2;
532
533 /* Nonzero if this chip is an XScale. */
534 extern int arm_arch_xscale;
535
536 /* Nonzero if tuning for XScale. */
537 extern int arm_tune_xscale;
538
539 /* Nonzero if tuning for stores via the write buffer. */
540 extern int arm_tune_wbuf;
541
542 /* Nonzero if tuning for Cortex-A9. */
543 extern int arm_tune_cortex_a9;
544
545 /* Nonzero if we should define __THUMB_INTERWORK__ in the
546 preprocessor.
547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550 extern int arm_cpp_interwork;
551
552 /* Nonzero if chip supports Thumb 1. */
553 extern int arm_arch_thumb1;
554
555 /* Nonzero if chip supports Thumb 2. */
556 extern int arm_arch_thumb2;
557
558 /* Nonzero if chip supports integer division instruction in ARM mode. */
559 extern int arm_arch_arm_hwdiv;
560
561 /* Nonzero if chip supports integer division instruction in Thumb mode. */
562 extern int arm_arch_thumb_hwdiv;
563
564 /* Nonzero if chip disallows volatile memory access in IT block. */
565 extern int arm_arch_no_volatile_ce;
566
567 /* Nonzero if we shouldn't use literal pools. */
568 #ifndef USED_FOR_TARGET
569 extern bool arm_disable_literal_pool;
570 #endif
571
572 /* Nonzero if chip supports the ARMv8 CRC instructions. */
573 extern int arm_arch_crc;
574
575 /* Nonzero if chip supports the ARMv8-M Security Extensions. */
576 extern int arm_arch_cmse;
577
578 /* Nonzero if chip supports the I8MM instructions. */
579 extern int arm_arch_i8mm;
580
581 /* Nonzero if chip supports the BFloat16 instructions. */
582 extern int arm_arch_bf16;
583
584 /* Nonzero if chip supports the Custom Datapath Extension. */
585 extern int arm_arch_cde;
586 extern int arm_arch_cde_coproc;
587 extern const int arm_arch_cde_coproc_bits[];
588 #define ARM_CDE_CONST_COPROC 7
589 #define ARM_CCDE_CONST_1 ((1 << 13) - 1)
590 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1)
591 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1)
592 #define ARM_VCDE_CONST_1 ((1 << 11) - 1)
593 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1)
594 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1)
595 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1)
596 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1)
597 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1)
598
599 #ifndef TARGET_DEFAULT
600 #define TARGET_DEFAULT (MASK_APCS_FRAME)
601 #endif
602
603 /* Nonzero if PIC code requires explicit qualifiers to generate
604 PLT and GOT relocs rather than the assembler doing so implicitly.
605 Subtargets can override these if required. */
606 #ifndef NEED_GOT_RELOC
607 #define NEED_GOT_RELOC 0
608 #endif
609 #ifndef NEED_PLT_RELOC
610 #define NEED_PLT_RELOC 0
611 #endif
612
613 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
614 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
615 #endif
616
617 /* Nonzero if we need to refer to the GOT with a PC-relative
618 offset. In other words, generate
619
620 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
621
622 rather than
623
624 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
625
626 The default is true, which matches NetBSD. Subtargets can
627 override this if required. */
628 #ifndef GOT_PCREL
629 #define GOT_PCREL 1
630 #endif
631
632 /* Target machine storage Layout. */
633
634 /* Nonzero if this chip provides Armv8.1-M Mainline
635 LOB (low overhead branch features) extension instructions. */
636 #define TARGET_HAVE_LOB (arm_arch8_1m_main)
637
638 /* Define this macro if it is advisable to hold scalars in registers
639 in a wider mode than that declared by the program. In such cases,
640 the value is constrained to be within the bounds of the declared
641 type, but kept valid in the wider mode. The signedness of the
642 extension may differ from that of the type. */
643
644 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
645 if (GET_MODE_CLASS (MODE) == MODE_INT \
646 && GET_MODE_SIZE (MODE) < 4) \
647 { \
648 (MODE) = SImode; \
649 }
650
651 /* Define this if most significant bit is lowest numbered
652 in instructions that operate on numbered bit-fields. */
653 #define BITS_BIG_ENDIAN 0
654
655 /* Define this if most significant byte of a word is the lowest numbered.
656 Most ARM processors are run in little endian mode, so that is the default.
657 If you want to have it run-time selectable, change the definition in a
658 cover file to be TARGET_BIG_ENDIAN. */
659 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
660
661 /* Define this if most significant word of a multiword number is the lowest
662 numbered. */
663 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
664
665 #define UNITS_PER_WORD 4
666
667 /* True if natural alignment is used for doubleword types. */
668 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
669
670 #define DOUBLEWORD_ALIGNMENT 64
671
672 #define PARM_BOUNDARY 32
673
674 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
675
676 #define PREFERRED_STACK_BOUNDARY \
677 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
678
679 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32)
680 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags))
681
682 /* The lowest bit is used to indicate Thumb-mode functions, so the
683 vbit must go into the delta field of pointers to member
684 functions. */
685 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
686
687 #define EMPTY_FIELD_BOUNDARY 32
688
689 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
690
691 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
692
693 /* XXX Blah -- this macro is used directly by libobjc. Since it
694 supports no vector modes, cut out the complexity and fall back
695 on BIGGEST_FIELD_ALIGNMENT. */
696 #ifdef IN_TARGET_LIBS
697 #define BIGGEST_FIELD_ALIGNMENT 64
698 #endif
699
700 /* Align definitions of arrays, unions and structures so that
701 initializations and copies can be made more efficient. This is not
702 ABI-changing, so it only affects places where we can see the
703 definition. Increasing the alignment tends to introduce padding,
704 so don't do this when optimizing for size/conserving stack space. */
705 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
706 (((COND) && ((ALIGN) < BITS_PER_WORD) \
707 && (TREE_CODE (EXP) == ARRAY_TYPE \
708 || TREE_CODE (EXP) == UNION_TYPE \
709 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
710
711 /* Align global data. */
712 #define DATA_ALIGNMENT(EXP, ALIGN) \
713 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
714
715 /* Similarly, make sure that objects on the stack are sensibly aligned. */
716 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
717 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
718
719 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
720 value set in previous versions of this toolchain was 8, which produces more
721 compact structures. The command line option -mstructure_size_boundary=<n>
722 can be used to change this value. For compatibility with the ARM SDK
723 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
724 0020D) page 2-20 says "Structures are aligned on word boundaries".
725 The AAPCS specifies a value of 8. */
726 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
727
728 /* This is the value used to initialize arm_structure_size_boundary. If a
729 particular arm target wants to change the default value it should change
730 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
731 for an example of this. */
732 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
733 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
734 #endif
735
736 /* Nonzero if move instructions will actually fail to work
737 when given unaligned data. */
738 #define STRICT_ALIGNMENT 1
739
740 /* wchar_t is unsigned under the AAPCS. */
741 #ifndef WCHAR_TYPE
742 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
743
744 #define WCHAR_TYPE_SIZE BITS_PER_WORD
745 #endif
746
747 /* Sized for fixed-point types. */
748
749 #define SHORT_FRACT_TYPE_SIZE 8
750 #define FRACT_TYPE_SIZE 16
751 #define LONG_FRACT_TYPE_SIZE 32
752 #define LONG_LONG_FRACT_TYPE_SIZE 64
753
754 #define SHORT_ACCUM_TYPE_SIZE 16
755 #define ACCUM_TYPE_SIZE 32
756 #define LONG_ACCUM_TYPE_SIZE 64
757 #define LONG_LONG_ACCUM_TYPE_SIZE 64
758
759 #define MAX_FIXED_MODE_SIZE 64
760
761 #ifndef SIZE_TYPE
762 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
763 #endif
764
765 #ifndef PTRDIFF_TYPE
766 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
767 #endif
768
769 /* AAPCS requires that structure alignment is affected by bitfields. */
770 #ifndef PCC_BITFIELD_TYPE_MATTERS
771 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
772 #endif
773
774 /* The maximum size of the sync library functions supported. */
775 #ifndef MAX_SYNC_LIBFUNC_SIZE
776 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD)
777 #endif
778
779
780 /* Standard register usage. */
781
782 /* Register allocation in ARM Procedure Call Standard
783 (S - saved over call, F - Frame-related).
784
785 r0 * argument word/integer result
786 r1-r3 argument word
787
788 r4-r8 S register variable
789 r9 S (rfp) register variable (real frame pointer)
790
791 r10 F S (sl) stack limit (used by -mapcs-stack-check)
792 r11 F S (fp) argument pointer
793 r12 (ip) temp workspace
794 r13 F S (sp) lower end of current stack frame
795 r14 (lr) link address/workspace
796 r15 F (pc) program counter
797
798 cc This is NOT a real register, but is used internally
799 to represent things that use or set the condition
800 codes.
801 sfp This isn't either. It is used during rtl generation
802 since the offset between the frame pointer and the
803 auto's isn't known until after register allocation.
804 afp Nor this, we only need this because of non-local
805 goto. Without it fp appears to be used and the
806 elimination code won't get rid of sfp. It tracks
807 fp exactly at all times.
808 apsrq Nor this, it is used to track operations on the Q bit
809 of APSR by ACLE saturating intrinsics.
810 apsrge Nor this, it is used to track operations on the GE bits
811 of APSR by ACLE SIMD32 intrinsics
812
813 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
814
815 /* s0-s15 VFP scratch (aka d0-d7).
816 s16-s31 S VFP variable (aka d8-d15).
817 vfpcc Not a real register. Represents the VFP condition
818 code flags.
819 vpr Used to represent MVE VPR predication.
820 ra_auth_code Pseudo register to save PAC. */
821
822 /* The stack backtrace structure is as follows:
823 fp points to here: | save code pointer | [fp]
824 | return link value | [fp, #-4]
825 | return sp value | [fp, #-8]
826 | return fp value | [fp, #-12]
827 [| saved r10 value |]
828 [| saved r9 value |]
829 [| saved r8 value |]
830 [| saved r7 value |]
831 [| saved r6 value |]
832 [| saved r5 value |]
833 [| saved r4 value |]
834 [| saved r3 value |]
835 [| saved r2 value |]
836 [| saved r1 value |]
837 [| saved r0 value |]
838 r0-r3 are not normally saved in a C function. */
839
840 /* 1 for registers that have pervasive standard uses
841 and are not available for the register allocator. */
842 #define FIXED_REGISTERS \
843 { \
844 /* Core regs. */ \
845 0,0,0,0,0,0,0,0, \
846 0,0,0,0,0,1,0,1, \
847 /* VFP regs. */ \
848 1,1,1,1,1,1,1,1, \
849 1,1,1,1,1,1,1,1, \
850 1,1,1,1,1,1,1,1, \
851 1,1,1,1,1,1,1,1, \
852 1,1,1,1,1,1,1,1, \
853 1,1,1,1,1,1,1,1, \
854 1,1,1,1,1,1,1,1, \
855 1,1,1,1,1,1,1,1, \
856 /* IWMMXT regs. */ \
857 1,1,1,1,1,1,1,1, \
858 1,1,1,1,1,1,1,1, \
859 1,1,1,1, \
860 /* Specials. */ \
861 1,1,1,1,1,1,1,1 \
862 }
863
864 /* 1 for registers not available across function calls.
865 These must include the FIXED_REGISTERS and also any
866 registers that can be used without being saved.
867 The latter must include the registers where values are returned
868 and the register where structure-value addresses are passed.
869 Aside from that, you can include as many other registers as you like.
870 The CC is not preserved over function calls on the ARM 6, so it is
871 easier to assume this for all. SFP is preserved, since FP is. */
872 #define CALL_USED_REGISTERS \
873 { \
874 /* Core regs. */ \
875 1,1,1,1,0,0,0,0, \
876 0,0,0,0,1,1,1,1, \
877 /* VFP Regs. */ \
878 1,1,1,1,1,1,1,1, \
879 1,1,1,1,1,1,1,1, \
880 1,1,1,1,1,1,1,1, \
881 1,1,1,1,1,1,1,1, \
882 1,1,1,1,1,1,1,1, \
883 1,1,1,1,1,1,1,1, \
884 1,1,1,1,1,1,1,1, \
885 1,1,1,1,1,1,1,1, \
886 /* IWMMXT regs. */ \
887 1,1,1,1,1,1,1,1, \
888 1,1,1,1,1,1,1,1, \
889 1,1,1,1, \
890 /* Specials. */ \
891 1,1,1,1,1,1,1,1 \
892 }
893
894 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
895 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
896 #endif
897
898 /* These are a couple of extensions to the formats accepted
899 by asm_fprintf:
900 %@ prints out ASM_COMMENT_START
901 %r prints out REGISTER_PREFIX reg_names[arg] */
902 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
903 case '@': \
904 fputs (ASM_COMMENT_START, FILE); \
905 break; \
906 \
907 case 'r': \
908 fputs (REGISTER_PREFIX, FILE); \
909 fputs (reg_names [va_arg (ARGS, int)], FILE); \
910 break;
911
912 /* Round X up to the nearest word. */
913 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
914
915 /* Convert fron bytes to ints. */
916 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
917
918 /* The number of (integer) registers required to hold a quantity of type MODE.
919 Also used for VFP registers. */
920 #define ARM_NUM_REGS(MODE) \
921 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
922
923 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
924 #define ARM_NUM_REGS2(MODE, TYPE) \
925 ARM_NUM_INTS ((MODE) == BLKmode ? \
926 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
927
928 /* The number of (integer) argument register available. */
929 #define NUM_ARG_REGS 4
930
931 /* And similarly for the VFP. */
932 #define NUM_VFP_ARG_REGS 16
933
934 /* Return the register number of the N'th (integer) argument. */
935 #define ARG_REGISTER(N) (N - 1)
936
937 /* Specify the registers used for certain standard purposes.
938 The values of these macros are register numbers. */
939
940 /* The number of the last argument register. */
941 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
942
943 /* The numbers of the Thumb register ranges. */
944 #define FIRST_LO_REGNUM 0
945 #define LAST_LO_REGNUM 7
946 #define FIRST_HI_REGNUM 8
947 #define LAST_HI_REGNUM 11
948
949 /* Overridden by config/arm/bpabi.h. */
950 #ifndef ARM_UNWIND_INFO
951 #define ARM_UNWIND_INFO 0
952 #endif
953
954 /* Use r0 and r1 to pass exception handling information. */
955 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
956
957 /* The register that holds the return address in exception handlers. */
958 #define ARM_EH_STACKADJ_REGNUM 2
959 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
960
961 #ifndef ARM_TARGET2_DWARF_FORMAT
962 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
963 #endif
964
965 /* ttype entries (the only interesting data references used)
966 use TARGET2 relocations. */
967 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
968 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
969 : DW_EH_PE_absptr)
970
971 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
972 as an invisible last argument (possible since varargs don't exist in
973 Pascal), so the following is not true. */
974 #define STATIC_CHAIN_REGNUM 12
975
976 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */
977 #define FDPIC_REGNUM 9
978
979 /* Define this to be where the real frame pointer is if it is not possible to
980 work out the offset between the frame pointer and the automatic variables
981 until after register allocation has taken place. FRAME_POINTER_REGNUM
982 should point to a special register that we will make sure is eliminated.
983
984 For the Thumb we have another problem. The TPCS defines the frame pointer
985 as r11, and GCC believes that it is always possible to use the frame pointer
986 as base register for addressing purposes. (See comments in
987 find_reloads_address()). But - the Thumb does not allow high registers,
988 including r11, to be used as base address registers. Hence our problem.
989
990 The solution used here, and in the old thumb port is to use r7 instead of
991 r11 as the hard frame pointer and to have special code to generate
992 backtrace structures on the stack (if required to do so via a command line
993 option) using r11. This is the only 'user visible' use of r11 as a frame
994 pointer. */
995 #define ARM_HARD_FRAME_POINTER_REGNUM 11
996 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
997
998 #define HARD_FRAME_POINTER_REGNUM \
999 (TARGET_ARM \
1000 ? ARM_HARD_FRAME_POINTER_REGNUM \
1001 : THUMB_HARD_FRAME_POINTER_REGNUM)
1002
1003 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1004 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1005
1006 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1007
1008 /* Register to use for pushing function arguments. */
1009 #define STACK_POINTER_REGNUM SP_REGNUM
1010
1011 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
1012 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
1013
1014 /* Need to sync with WCGR in iwmmxt.md. */
1015 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
1016 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
1017
1018 #define IS_IWMMXT_REGNUM(REGNUM) \
1019 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1020 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1021 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1022
1023 /* Base register for access to local variables of the function. */
1024 #define FRAME_POINTER_REGNUM 102
1025
1026 /* Base register for access to arguments of the function. */
1027 #define ARG_POINTER_REGNUM 103
1028
1029 #define FIRST_VFP_REGNUM 16
1030 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
1031 #define LAST_VFP_REGNUM \
1032 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1033
1034 #define IS_VFP_REGNUM(REGNUM) \
1035 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1036
1037 /* VFP registers are split into two types: those defined by VFP versions < 3
1038 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1039 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1040 in various parts of the backend, we implement as "fake" single-precision
1041 registers (which would be S32-S63, but cannot be used in that way). The
1042 following macros define these ranges of registers. */
1043 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
1044 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
1045 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
1046
1047 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1048 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1049
1050 /* DFmode values are only valid in even register pairs. */
1051 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1052 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1053
1054 /* Neon Quad values must start at a multiple of four registers. */
1055 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1056 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1057
1058 /* Neon structures of vectors must be in even register pairs and there
1059 must be enough registers available. Because of various patterns
1060 requiring quad registers, we require them to start at a multiple of
1061 four. */
1062 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1063 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1064 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1065
1066 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
1067 + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
1068 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1069 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1070 #define FIRST_PSEUDO_REGISTER 108
1071
1072 #define DWARF_PAC_REGNUM 143
1073
1074 #define DEBUGGER_REGNO(REGNO) arm_debugger_regno (REGNO)
1075
1076 /* Value should be nonzero if functions must have frame pointers.
1077 Zero means the frame pointer need not be set up (and parms may be accessed
1078 via the stack pointer) in functions that seem suitable.
1079 If we have to have a frame pointer we might as well make use of it.
1080 APCS says that the frame pointer does not need to be pushed in leaf
1081 functions, or simple tail call functions. */
1082
1083 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1084 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1085 #endif
1086
1087 #define VALID_IWMMXT_REG_MODE(MODE) \
1088 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1089
1090 /* Modes valid for Neon D registers. */
1091 #define VALID_NEON_DREG_MODE(MODE) \
1092 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1093 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \
1094 || (MODE) == V4BFmode)
1095
1096 /* Modes valid for Neon Q registers. */
1097 #define VALID_NEON_QREG_MODE(MODE) \
1098 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1099 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \
1100 || (MODE) == V8BFmode)
1101
1102 #define VALID_MVE_MODE(MODE) \
1103 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \
1104 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \
1105 || (MODE) == V2DFmode)
1106
1107 #define VALID_MVE_PRED_MODE(MODE) \
1108 ((MODE) == HImode \
1109 || (MODE) == V16BImode || (MODE) == V8BImode || (MODE) == V4BImode \
1110 || (MODE) == V2QImode)
1111
1112 #define VALID_MVE_SI_MODE(MODE) \
1113 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \
1114 || (MODE) == V16QImode)
1115
1116 /* Modes used in MVE's narrowing stores or widening loads. */
1117 #define MVE_STN_LDW_MODE(MODE) \
1118 ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode)
1119
1120 #define VALID_MVE_SF_MODE(MODE) \
1121 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode)
1122
1123 /* Structure modes valid for Neon registers. */
1124 #define VALID_NEON_STRUCT_MODE(MODE) \
1125 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1126 || (MODE) == CImode || (MODE) == XImode)
1127
1128 #define VALID_MVE_STRUCT_MODE(MODE) \
1129 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode)
1130
1131 /* The conditions under which vector modes are supported for general
1132 arithmetic using Neon. */
1133
1134 #define ARM_HAVE_NEON_V8QI_ARITH TARGET_NEON
1135 #define ARM_HAVE_NEON_V4HI_ARITH TARGET_NEON
1136 #define ARM_HAVE_NEON_V2SI_ARITH TARGET_NEON
1137
1138 #define ARM_HAVE_NEON_V16QI_ARITH TARGET_NEON
1139 #define ARM_HAVE_NEON_V8HI_ARITH TARGET_NEON
1140 #define ARM_HAVE_NEON_V4SI_ARITH TARGET_NEON
1141 #define ARM_HAVE_NEON_V2DI_ARITH TARGET_NEON
1142
1143 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */
1144 #define ARM_HAVE_NEON_V4HF_ARITH TARGET_NEON_FP16INST
1145 #define ARM_HAVE_NEON_V8HF_ARITH TARGET_NEON_FP16INST
1146
1147 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can
1148 only use them for general arithmetic when -funsafe-math-optimizations
1149 is in effect. */
1150 #define ARM_HAVE_NEON_V2SF_ARITH \
1151 (TARGET_NEON && flag_unsafe_math_optimizations)
1152 #define ARM_HAVE_NEON_V4SF_ARITH ARM_HAVE_NEON_V2SF_ARITH
1153
1154 /* The conditions under which vector modes are supported for general
1155 arithmetic by any vector extension. */
1156
1157 #define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT)
1158 #define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT)
1159 #define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT)
1160
1161 #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE)
1162 #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE)
1163 #define ARM_HAVE_V4SI_ARITH (ARM_HAVE_NEON_V4SI_ARITH || TARGET_HAVE_MVE)
1164 #define ARM_HAVE_V2DI_ARITH ARM_HAVE_NEON_V2DI_ARITH
1165
1166 #define ARM_HAVE_V4HF_ARITH ARM_HAVE_NEON_V4HF_ARITH
1167 #define ARM_HAVE_V2SF_ARITH ARM_HAVE_NEON_V2SF_ARITH
1168
1169 #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT)
1170 #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT)
1171
1172 /* The conditions under which vector modes are supported by load/store
1173 instructions using Neon. */
1174
1175 #define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON
1176 #define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON
1177 #define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON
1178 #define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON
1179 #define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON
1180 #define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON
1181 #define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST
1182 #define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST
1183 #define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD
1184 #define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD
1185 #define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON
1186 #define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON
1187 #define ARM_HAVE_NEON_DI_LDST TARGET_NEON
1188 #define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON
1189
1190 /* The conditions under which vector modes are supported by load/store
1191 instructions by any vector extension. */
1192
1193 #define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT)
1194 #define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT)
1195 #define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT)
1196
1197 #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE)
1198 #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE)
1199 #define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE)
1200 #define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST
1201 #define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST
1202
1203 #define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST
1204 #define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST
1205
1206 #define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST
1207 #define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST
1208
1209 #define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT)
1210 #define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT)
1211
1212 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1213 extern int arm_regs_in_sequence[];
1214
1215 /* The order in which register should be allocated. It is good to use ip
1216 since no saving is required (though calls clobber it) and it never contains
1217 function parameters. It is quite good to use lr since other calls may
1218 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1219 least likely to contain a function parameter; in addition results are
1220 returned in r0.
1221 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1222 then D8-D15. The reason for doing this is to attempt to reduce register
1223 pressure when both single- and double-precision registers are used in a
1224 function. */
1225
1226 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1227 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1228 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1229
1230 #define REG_ALLOC_ORDER \
1231 { \
1232 /* General registers. */ \
1233 3, 2, 1, 0, 12, 14, 4, 5, \
1234 6, 7, 8, 9, 10, 11, \
1235 /* High VFP registers. */ \
1236 VREG(32), VREG(33), VREG(34), VREG(35), \
1237 VREG(36), VREG(37), VREG(38), VREG(39), \
1238 VREG(40), VREG(41), VREG(42), VREG(43), \
1239 VREG(44), VREG(45), VREG(46), VREG(47), \
1240 VREG(48), VREG(49), VREG(50), VREG(51), \
1241 VREG(52), VREG(53), VREG(54), VREG(55), \
1242 VREG(56), VREG(57), VREG(58), VREG(59), \
1243 VREG(60), VREG(61), VREG(62), VREG(63), \
1244 /* VFP argument registers. */ \
1245 VREG(15), VREG(14), VREG(13), VREG(12), \
1246 VREG(11), VREG(10), VREG(9), VREG(8), \
1247 VREG(7), VREG(6), VREG(5), VREG(4), \
1248 VREG(3), VREG(2), VREG(1), VREG(0), \
1249 /* VFP call-saved registers. */ \
1250 VREG(16), VREG(17), VREG(18), VREG(19), \
1251 VREG(20), VREG(21), VREG(22), VREG(23), \
1252 VREG(24), VREG(25), VREG(26), VREG(27), \
1253 VREG(28), VREG(29), VREG(30), VREG(31), \
1254 /* IWMMX registers. */ \
1255 WREG(0), WREG(1), WREG(2), WREG(3), \
1256 WREG(4), WREG(5), WREG(6), WREG(7), \
1257 WREG(8), WREG(9), WREG(10), WREG(11), \
1258 WREG(12), WREG(13), WREG(14), WREG(15), \
1259 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1260 /* Registers not for general use. */ \
1261 CC_REGNUM, VFPCC_REGNUM, \
1262 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1263 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
1264 APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
1265 }
1266
1267 #define IS_VPR_REGNUM(REGNUM) \
1268 ((REGNUM) == VPR_REGNUM)
1269
1270 #define IS_PAC_REGNUM(REGNUM) \
1271 ((REGNUM) == RA_AUTH_CODE)
1272
1273 /* Use different register alloc ordering for Thumb. */
1274 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1275
1276 /* Tell IRA to use the order we define when optimizing for size. */
1277 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun)
1278
1279 /* Interrupt functions can only use registers that have already been
1280 saved by the prologue, even if they would normally be
1281 call-clobbered. */
1282 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1283 (! IS_INTERRUPT (cfun->machine->func_type) || \
1284 df_regs_ever_live_p (DST))
1285
1286 /* Register and constant classes. */
1287
1288 /* Register classes. */
1289 enum reg_class
1290 {
1291 NO_REGS,
1292 LO_REGS,
1293 STACK_REG,
1294 BASE_REGS,
1295 HI_REGS,
1296 CALLER_SAVE_REGS,
1297 EVEN_REG,
1298 GENERAL_REGS,
1299 CORE_REGS,
1300 VFP_D0_D7_REGS,
1301 VFP_LO_REGS,
1302 VFP_HI_REGS,
1303 VFP_REGS,
1304 IWMMXT_REGS,
1305 IWMMXT_GR_REGS,
1306 CC_REG,
1307 VFPCC_REG,
1308 SFP_REG,
1309 AFP_REG,
1310 VPR_REG,
1311 PAC_REG,
1312 GENERAL_AND_VPR_REGS,
1313 ALL_REGS,
1314 LIM_REG_CLASSES
1315 };
1316
1317 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1318
1319 /* Give names of register classes as strings for dump file. */
1320 #define REG_CLASS_NAMES \
1321 { \
1322 "NO_REGS", \
1323 "LO_REGS", \
1324 "STACK_REG", \
1325 "BASE_REGS", \
1326 "HI_REGS", \
1327 "CALLER_SAVE_REGS", \
1328 "EVEN_REG", \
1329 "GENERAL_REGS", \
1330 "CORE_REGS", \
1331 "VFP_D0_D7_REGS", \
1332 "VFP_LO_REGS", \
1333 "VFP_HI_REGS", \
1334 "VFP_REGS", \
1335 "IWMMXT_REGS", \
1336 "IWMMXT_GR_REGS", \
1337 "CC_REG", \
1338 "VFPCC_REG", \
1339 "SFP_REG", \
1340 "AFP_REG", \
1341 "VPR_REG", \
1342 "PAC_REG", \
1343 "GENERAL_AND_VPR_REGS", \
1344 "ALL_REGS" \
1345 }
1346
1347 /* Define which registers fit in which classes.
1348 This is an initializer for a vector of HARD_REG_SET
1349 of length N_REG_CLASSES. */
1350 #define REG_CLASS_CONTENTS \
1351 { \
1352 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1353 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1354 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1355 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1356 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1357 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
1358 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \
1359 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1360 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1361 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1362 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1363 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1364 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1365 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1366 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1367 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1368 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1369 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1370 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1371 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
1372 { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \
1373 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
1374 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \
1375 }
1376
1377 #define FP_SYSREGS \
1378 DEF_FP_SYSREG (FPSCR) \
1379 DEF_FP_SYSREG (FPSCR_nzcvqc) \
1380 DEF_FP_SYSREG (VPR) \
1381 DEF_FP_SYSREG (P0) \
1382 DEF_FP_SYSREG (FPCXTNS) \
1383 DEF_FP_SYSREG (FPCXTS)
1384
1385 #define DEF_FP_SYSREG(reg) reg ## _ENUM,
1386 enum vfp_sysregs_encoding {
1387 FP_SYSREGS
1388 NB_FP_SYSREGS
1389 };
1390 #undef DEF_FP_SYSREG
1391 extern const char *fp_sysreg_names[NB_FP_SYSREGS];
1392
1393 /* Any of the VFP register classes. */
1394 #define IS_VFP_CLASS(X) \
1395 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1396 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1397
1398 /* The same information, inverted:
1399 Return the class number of the smallest class containing
1400 reg number REGNO. This could be a conditional expression
1401 or could index an array. */
1402 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1403
1404 /* The class value for index registers, and the one for base regs. */
1405 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1406 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1407
1408 /* For the Thumb the high registers cannot be used as base registers
1409 when addressing quantities in QI or HI mode; if we don't know the
1410 mode, then we must be conservative. For MVE we need to load from
1411 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */
1412 #define MODE_BASE_REG_CLASS(MODE) \
1413 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \
1414 :(TARGET_32BIT ? CORE_REGS \
1415 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \
1416 : LO_REGS))
1417
1418 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS
1419 instead of BASE_REGS. */
1420 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1421
1422 /* When this hook returns true for MODE, the compiler allows
1423 registers explicitly used in the rtl to be used as spill registers
1424 but prevents the compiler from extending the lifetime of these
1425 registers. */
1426 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1427 arm_small_register_classes_for_mode_p
1428
1429 /* Must leave BASE_REGS reloads alone */
1430 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1431 (lra_in_progress ? NO_REGS \
1432 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1433 ? ((true_regnum (X) == -1 ? LO_REGS \
1434 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
1435 : NO_REGS)) \
1436 : NO_REGS))
1437
1438 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1439 (lra_in_progress ? NO_REGS \
1440 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1441 ? ((true_regnum (X) == -1 ? LO_REGS \
1442 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
1443 : NO_REGS)) \
1444 : NO_REGS)
1445
1446 /* Return the register class of a scratch register needed to copy IN into
1447 or out of a register in CLASS in MODE. If it can be done directly,
1448 NO_REGS is returned. */
1449 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1450 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1451 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1452 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1453 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1454 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1455 : TARGET_32BIT \
1456 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1457 ? GENERAL_REGS : NO_REGS) \
1458 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1459
1460 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1461 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1462 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1463 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1464 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1465 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1466 coproc_secondary_reload_class (MODE, X, TRUE) : \
1467 (TARGET_32BIT ? \
1468 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1469 && CONSTANT_P (X)) \
1470 ? GENERAL_REGS : \
1471 (((MODE) == HImode && ! arm_arch4 \
1472 && (MEM_P (X) \
1473 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1474 && true_regnum (X) == -1))) \
1475 ? GENERAL_REGS : NO_REGS) \
1476 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1477
1478 /* Return the maximum number of consecutive registers
1479 needed to represent mode MODE in a register of class CLASS.
1480 ARM regs are UNITS_PER_WORD bits.
1481 FIXME: Is this true for iWMMX? */
1482 #define CLASS_MAX_NREGS(CLASS, MODE) \
1483 (CLASS == VPR_REG) \
1484 ? CEIL (GET_MODE_SIZE (MODE), 2) \
1485 : (ARM_NUM_REGS (MODE))
1486
1487 /* If defined, gives a class of registers that cannot be used as the
1488 operand of a SUBREG that changes the mode of the object illegally. */
1489
1490 /* Stack layout; function entry, exit and calling. */
1491
1492 /* Define this if pushing a word on the stack
1493 makes the stack pointer a smaller address. */
1494 #define STACK_GROWS_DOWNWARD 1
1495
1496 /* Define this to nonzero if the nominal address of the stack frame
1497 is at the high-address end of the local variables;
1498 that is, each additional local variable allocated
1499 goes at a more negative offset in the frame. */
1500 #define FRAME_GROWS_DOWNWARD 1
1501
1502 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1503 When present, it is one word in size, and sits at the top of the frame,
1504 between the soft frame pointer and either r7 or r11.
1505
1506 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1507 and only then if some outgoing arguments are passed on the stack. It would
1508 be tempting to also check whether the stack arguments are passed by indirect
1509 calls, but there seems to be no reason in principle why a post-reload pass
1510 couldn't convert a direct call into an indirect one. */
1511 #define CALLER_INTERWORKING_SLOT_SIZE \
1512 (TARGET_CALLER_INTERWORKING \
1513 && maybe_ne (crtl->outgoing_args_size, 0) \
1514 ? UNITS_PER_WORD : 0)
1515
1516 /* If we generate an insn to push BYTES bytes,
1517 this says how many the stack pointer really advances by. */
1518 /* The push insns do not do this rounding implicitly.
1519 So don't define this. */
1520 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1521
1522 /* Define this if the maximum size of all the outgoing args is to be
1523 accumulated and pushed during the prologue. The amount can be
1524 found in the variable crtl->outgoing_args_size. */
1525 #define ACCUMULATE_OUTGOING_ARGS 1
1526
1527 /* Offset of first parameter from the argument pointer register value. */
1528 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1529
1530 /* Amount of memory needed for an untyped call to save all possible return
1531 registers. */
1532 #define APPLY_RESULT_SIZE arm_apply_result_size()
1533
1534 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1535 values must be in memory. On the ARM, they need only do so if larger
1536 than a word, or if they contain elements offset from zero in the struct. */
1537 #define DEFAULT_PCC_STRUCT_RETURN 0
1538
1539 /* These bits describe the different types of function supported
1540 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1541 normal function and an interworked function, for example. Knowing the
1542 type of a function is important for determining its prologue and
1543 epilogue sequences.
1544 Note value 7 is currently unassigned. Also note that the interrupt
1545 function types all have bit 2 set, so that they can be tested for easily.
1546 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1547 machine_function structure is initialized (to zero) func_type will
1548 default to unknown. This will force the first use of arm_current_func_type
1549 to call arm_compute_func_type. */
1550 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1551 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1552 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1553 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1554 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1555 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1556
1557 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1558
1559 /* In addition functions can have several type modifiers,
1560 outlined by these bit masks: */
1561 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1562 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1563 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1564 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1565 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1566 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */
1567
1568 /* Some macros to test these flags. */
1569 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1570 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1571 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1572 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1573 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1574 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1575 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY)
1576
1577
1578 /* Structure used to hold the function stack frame layout. Offsets are
1579 relative to the stack pointer on function entry. Positive offsets are
1580 in the direction of stack growth.
1581 Only soft_frame is used in thumb mode. */
1582
1583 typedef struct GTY(()) arm_stack_offsets
1584 {
1585 int saved_args; /* ARG_POINTER_REGNUM. */
1586 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1587 int saved_regs;
1588 int soft_frame; /* FRAME_POINTER_REGNUM. */
1589 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1590 int outgoing_args; /* STACK_POINTER_REGNUM. */
1591 unsigned int saved_regs_mask;
1592 }
1593 arm_stack_offsets;
1594
1595 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET)
1596 /* A C structure for machine-specific, per-function data.
1597 This is added to the cfun structure. */
1598 typedef struct GTY(()) machine_function
1599 {
1600 /* Additional stack adjustment in __builtin_eh_throw. */
1601 rtx eh_epilogue_sp_ofs;
1602 /* Records if LR has to be saved for far jumps. */
1603 int far_jump_used;
1604 /* Records if ARG_POINTER was ever live. */
1605 int arg_pointer_live;
1606 /* Records if the save of LR has been eliminated. */
1607 int lr_save_eliminated;
1608 /* The size of the stack frame. Only valid after reload. */
1609 arm_stack_offsets stack_offsets;
1610 /* Records the type of the current function. */
1611 unsigned long func_type;
1612 /* Record if the function has a variable argument list. */
1613 int uses_anonymous_args;
1614 /* Records if sibcalls are blocked because an argument
1615 register is needed to preserve stack alignment. */
1616 int sibcall_blocked;
1617 /* The PIC register for this function. This might be a pseudo. */
1618 rtx pic_reg;
1619 /* Labels for per-function Thumb call-via stubs. One per potential calling
1620 register. We can never call via LR or PC. We can call via SP if a
1621 trampoline happens to be on the top of the stack. */
1622 rtx call_via[14];
1623 /* Set to 1 when a return insn is output, this means that the epilogue
1624 is not needed. */
1625 int return_used_this_function;
1626 /* When outputting Thumb-1 code, record the last insn that provides
1627 information about condition codes, and the comparison operands. */
1628 rtx thumb1_cc_insn;
1629 rtx thumb1_cc_op0;
1630 rtx thumb1_cc_op1;
1631 /* Also record the CC mode that is supported. */
1632 machine_mode thumb1_cc_mode;
1633 /* Set to 1 after arm_reorg has started. */
1634 int after_arm_reorg;
1635 /* The number of bytes used to store the static chain register on the
1636 stack, above the stack frame. */
1637 int static_chain_stack_bytes;
1638 /* Set to 1 when pointer authentication operation uses value of SP other
1639 than the incoming stack pointer value. */
1640 int pacspval_needed;
1641 }
1642 machine_function;
1643 #endif
1644
1645 #define ARM_Q_BIT_READ (arm_q_bit_access ())
1646 #define ARM_GE_BITS_READ (arm_ge_bits_access ())
1647
1648 /* As in the machine_function, a global set of call-via labels, for code
1649 that is in text_section. */
1650 extern GTY(()) rtx thumb_call_via_label[14];
1651
1652 /* The number of potential ways of assigning to a co-processor. */
1653 #define ARM_NUM_COPROC_SLOTS 1
1654
1655 /* Enumeration of procedure calling standard variants. We don't really
1656 support all of these yet. */
1657 enum arm_pcs
1658 {
1659 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1660 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1661 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1662 /* This must be the last AAPCS variant. */
1663 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1664 ARM_PCS_ATPCS, /* ATPCS. */
1665 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1666 ARM_PCS_UNKNOWN
1667 };
1668
1669 /* Default procedure calling standard of current compilation unit. */
1670 extern enum arm_pcs arm_pcs_default;
1671
1672 #if !defined (USED_FOR_TARGET)
1673 /* A C type for declaring a variable that is used as the first argument of
1674 `FUNCTION_ARG' and other related values. */
1675 typedef struct
1676 {
1677 /* This is the number of registers of arguments scanned so far. */
1678 int nregs;
1679 /* This is the number of iWMMXt register arguments scanned so far. */
1680 int iwmmxt_nregs;
1681 int named_count;
1682 int nargs;
1683 /* Which procedure call variant to use for this call. */
1684 enum arm_pcs pcs_variant;
1685
1686 /* AAPCS related state tracking. */
1687 int aapcs_arg_processed; /* No need to lay out this argument again. */
1688 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1689 this argument, or -1 if using core
1690 registers. */
1691 int aapcs_ncrn;
1692 int aapcs_next_ncrn;
1693 rtx aapcs_reg; /* Register assigned to this argument. */
1694 int aapcs_partial; /* How many bytes are passed in regs (if
1695 split between core regs and stack.
1696 Zero otherwise. */
1697 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1698 int can_split; /* Argument can be split between core regs
1699 and the stack. */
1700 /* Private data for tracking VFP register allocation */
1701 unsigned aapcs_vfp_regs_free;
1702 unsigned aapcs_vfp_reg_alloc;
1703 int aapcs_vfp_rcount;
1704 MACHMODE aapcs_vfp_rmode;
1705 } CUMULATIVE_ARGS;
1706 #endif
1707
1708 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1709 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
1710
1711 /* For AAPCS, padding should never be below the argument. For other ABIs,
1712 * mimic the default. */
1713 #define PAD_VARARGS_DOWN \
1714 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1715
1716 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1717 for a call to a function whose data type is FNTYPE.
1718 For a library call, FNTYPE is 0.
1719 On the ARM, the offset starts at 0. */
1720 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1721 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1722
1723 /* 1 if N is a possible register number for function argument passing.
1724 On the ARM, r0-r3 are used to pass args. */
1725 #define FUNCTION_ARG_REGNO_P(REGNO) \
1726 (IN_RANGE ((REGNO), 0, 3) \
1727 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \
1728 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1729 || (TARGET_IWMMXT_ABI \
1730 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1731
1732
1733 /* If your target environment doesn't prefix user functions with an
1734 underscore, you may wish to re-define this to prevent any conflicts. */
1735 #ifndef ARM_MCOUNT_NAME
1736 #define ARM_MCOUNT_NAME "*mcount"
1737 #endif
1738
1739 /* Call the function profiler with a given profile label. The Acorn
1740 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1741 On the ARM the full profile code will look like:
1742 .data
1743 LP1
1744 .word 0
1745 .text
1746 mov ip, lr
1747 bl mcount
1748 .word LP1
1749
1750 profile_function() in final.cc outputs the .data section, FUNCTION_PROFILER
1751 will output the .text section.
1752
1753 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1754 ``prof'' doesn't seem to mind about this!
1755
1756 Note - this version of the code is designed to work in both ARM and
1757 Thumb modes. */
1758 #ifndef ARM_FUNCTION_PROFILER
1759 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1760 { \
1761 char temp[20]; \
1762 rtx sym; \
1763 \
1764 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1765 IP_REGNUM, LR_REGNUM); \
1766 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1767 fputc ('\n', STREAM); \
1768 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1769 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1770 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1771 }
1772 #endif
1773
1774 #ifdef THUMB_FUNCTION_PROFILER
1775 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1776 if (TARGET_ARM) \
1777 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1778 else \
1779 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1780 #else
1781 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1782 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1783 #endif
1784
1785 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1786 the stack pointer does not matter. The value is tested only in
1787 functions that have frame pointers.
1788 No definition is equivalent to always zero.
1789
1790 On the ARM, the function epilogue recovers the stack pointer from the
1791 frame. */
1792 #define EXIT_IGNORE_STACK 1
1793
1794 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
1795
1796 /* Determine if the epilogue should be output as RTL.
1797 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1798 #define USE_RETURN_INSN(ISCOND) \
1799 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1800
1801 /* Definitions for register eliminations.
1802
1803 This is an array of structures. Each structure initializes one pair
1804 of eliminable registers. The "from" register number is given first,
1805 followed by "to". Eliminations of the same "from" register are listed
1806 in order of preference.
1807
1808 We have two registers that can be eliminated on the ARM. First, the
1809 arg pointer register can often be eliminated in favor of the stack
1810 pointer register. Secondly, the pseudo frame pointer register can always
1811 be eliminated; it is replaced with either the stack or the real frame
1812 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1813 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1814
1815 #define ELIMINABLE_REGS \
1816 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1817 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1818 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1819 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1820 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1821 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1822 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1823
1824 /* Define the offset between two registers, one to be eliminated, and the
1825 other its replacement, at the start of a routine. */
1826 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1827 if (TARGET_ARM) \
1828 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1829 else \
1830 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1831
1832 /* Special case handling of the location of arguments passed on the stack. */
1833 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1834
1835 /* Initialize data used by insn expanders. This is called from insn_emit,
1836 once for every function before code is generated. */
1837 #define INIT_EXPANDERS arm_init_expanders ()
1838
1839 /* Length in units of the trampoline for entering a nested function. */
1840 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20))
1841
1842 /* Alignment required for a trampoline in bits. */
1843 #define TRAMPOLINE_ALIGNMENT 32
1844
1845 /* Addressing modes, and classification of registers for them. */
1846 #define HAVE_POST_INCREMENT 1
1847 #define HAVE_PRE_INCREMENT TARGET_32BIT
1848 #define HAVE_POST_DECREMENT TARGET_32BIT
1849 #define HAVE_PRE_DECREMENT TARGET_32BIT
1850 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1851 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1852 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1853 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1854
1855 enum arm_auto_incmodes
1856 {
1857 ARM_POST_INC,
1858 ARM_PRE_INC,
1859 ARM_POST_DEC,
1860 ARM_PRE_DEC
1861 };
1862
1863 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1864 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1865 #define USE_LOAD_POST_INCREMENT(mode) \
1866 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1867 #define USE_LOAD_PRE_INCREMENT(mode) \
1868 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1869 #define USE_LOAD_POST_DECREMENT(mode) \
1870 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1871 #define USE_LOAD_PRE_DECREMENT(mode) \
1872 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1873
1874 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1875 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1876 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1877 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1878
1879 /* Macros to check register numbers against specific register classes. */
1880
1881 /* These assume that REGNO is a hard or pseudo reg number.
1882 They give nonzero only if REGNO is a hard reg of the suitable class
1883 or a pseudo reg currently allocated to a suitable hard reg. */
1884 #define TEST_REGNO(R, TEST, VALUE) \
1885 ((R TEST VALUE) \
1886 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE)))
1887
1888 /* Don't allow the pc to be used. */
1889 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1890 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1891 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1892 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1893
1894 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1895 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1896 || (GET_MODE_SIZE (MODE) >= 4 \
1897 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1898
1899 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1900 (TARGET_THUMB1 \
1901 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1902 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1903
1904 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1905 For Thumb, we cannot use SP + reg, so reject SP. */
1906 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1907 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1908
1909 /* For ARM code, we don't care about the mode, but for Thumb, the index
1910 must be suitable for use in a QImode load. */
1911 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1912 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1913 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1914
1915 /* Maximum number of registers that can appear in a valid memory address.
1916 Shifts in addresses can't be by a register. */
1917 #define MAX_REGS_PER_ADDRESS 2
1918
1919 /* Recognize any constant value that is a valid address. */
1920 /* XXX We can address any constant, eventually... */
1921 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1922 #define CONSTANT_ADDRESS_P(X) \
1923 (GET_CODE (X) == SYMBOL_REF \
1924 && (CONSTANT_POOL_ADDRESS_P (X) \
1925 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1926
1927 /* True if SYMBOL + OFFSET constants must refer to something within
1928 SYMBOL's section. */
1929 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1930
1931 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1932 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1933 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1934 #endif
1935
1936 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1937 #define SUBTARGET_NAME_ENCODING_LENGTHS
1938 #endif
1939
1940 /* This is a C fragment for the inside of a switch statement.
1941 Each case label should return the number of characters to
1942 be stripped from the start of a function's name, if that
1943 name starts with the indicated character. */
1944 #define ARM_NAME_ENCODING_LENGTHS \
1945 case '*': return 1; \
1946 SUBTARGET_NAME_ENCODING_LENGTHS
1947
1948 /* This is how to output a reference to a user-level label named NAME.
1949 `assemble_name' uses this. */
1950 #undef ASM_OUTPUT_LABELREF
1951 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1952 arm_asm_output_labelref (FILE, NAME)
1953
1954 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1955 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1956 if (TARGET_THUMB2) \
1957 thumb2_asm_output_opcode (STREAM);
1958
1959 /* The EABI specifies that constructors should go in .init_array.
1960 Other targets use .ctors for compatibility. */
1961 #ifndef ARM_EABI_CTORS_SECTION_OP
1962 #define ARM_EABI_CTORS_SECTION_OP \
1963 "\t.section\t.init_array,\"aw\",%init_array"
1964 #endif
1965 #ifndef ARM_EABI_DTORS_SECTION_OP
1966 #define ARM_EABI_DTORS_SECTION_OP \
1967 "\t.section\t.fini_array,\"aw\",%fini_array"
1968 #endif
1969 #define ARM_CTORS_SECTION_OP \
1970 "\t.section\t.ctors,\"aw\",%progbits"
1971 #define ARM_DTORS_SECTION_OP \
1972 "\t.section\t.dtors,\"aw\",%progbits"
1973
1974 /* Define CTORS_SECTION_ASM_OP. */
1975 #undef CTORS_SECTION_ASM_OP
1976 #undef DTORS_SECTION_ASM_OP
1977 #ifndef IN_LIBGCC2
1978 # define CTORS_SECTION_ASM_OP \
1979 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1980 # define DTORS_SECTION_ASM_OP \
1981 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1982 #else /* !defined (IN_LIBGCC2) */
1983 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1984 so we cannot use the definition above. */
1985 # ifdef __ARM_EABI__
1986 /* The .ctors section is not part of the EABI, so we do not define
1987 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1988 from trying to use it. We do define it when doing normal
1989 compilation, as .init_array can be used instead of .ctors. */
1990 /* There is no need to emit begin or end markers when using
1991 init_array; the dynamic linker will compute the size of the
1992 array itself based on special symbols created by the static
1993 linker. However, we do need to arrange to set up
1994 exception-handling here. */
1995 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1996 # define CTOR_LIST_END /* empty */
1997 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1998 # define DTOR_LIST_END /* empty */
1999 # else /* !defined (__ARM_EABI__) */
2000 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2001 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2002 # endif /* !defined (__ARM_EABI__) */
2003 #endif /* !defined (IN_LIBCC2) */
2004
2005 /* True if the operating system can merge entities with vague linkage
2006 (e.g., symbols in COMDAT group) during dynamic linking. */
2007 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2008 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2009 #endif
2010
2011 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2012
2013 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2014 and check its validity for a certain class.
2015 We have two alternate definitions for each of them.
2016 The usual definition accepts all pseudo regs; the other rejects
2017 them unless they have been allocated suitable hard regs.
2018 The symbol REG_OK_STRICT causes the latter definition to be used.
2019 Thumb-2 has the same restrictions as arm. */
2020 #ifndef REG_OK_STRICT
2021
2022 #define ARM_REG_OK_FOR_BASE_P(X) \
2023 (REGNO (X) <= LAST_ARM_REGNUM \
2024 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2025 || REGNO (X) == FRAME_POINTER_REGNUM \
2026 || REGNO (X) == ARG_POINTER_REGNUM)
2027
2028 #define ARM_REG_OK_FOR_INDEX_P(X) \
2029 ((REGNO (X) <= LAST_ARM_REGNUM \
2030 && REGNO (X) != STACK_POINTER_REGNUM) \
2031 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2032 || REGNO (X) == FRAME_POINTER_REGNUM \
2033 || REGNO (X) == ARG_POINTER_REGNUM)
2034
2035 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2036 (REGNO (X) <= LAST_LO_REGNUM \
2037 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2038 || (GET_MODE_SIZE (MODE) >= 4 \
2039 && (REGNO (X) == STACK_POINTER_REGNUM \
2040 || (X) == hard_frame_pointer_rtx \
2041 || (X) == arg_pointer_rtx)))
2042
2043 #define REG_STRICT_P 0
2044
2045 #else /* REG_OK_STRICT */
2046
2047 #define ARM_REG_OK_FOR_BASE_P(X) \
2048 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2049
2050 #define ARM_REG_OK_FOR_INDEX_P(X) \
2051 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2052
2053 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2054 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2055
2056 #define REG_STRICT_P 1
2057
2058 #endif /* REG_OK_STRICT */
2059
2060 /* Now define some helpers in terms of the above. */
2061
2062 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2063 (TARGET_THUMB1 \
2064 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2065 : ARM_REG_OK_FOR_BASE_P (X))
2066
2067 /* For 16-bit Thumb, a valid index register is anything that can be used in
2068 a byte load instruction. */
2069 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2070 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2071
2072 /* Nonzero if X is a hard reg that can be used as an index
2073 or if it is a pseudo reg. On the Thumb, the stack pointer
2074 is not suitable. */
2075 #define REG_OK_FOR_INDEX_P(X) \
2076 (TARGET_THUMB1 \
2077 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2078 : ARM_REG_OK_FOR_INDEX_P (X))
2079
2080 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2081 For Thumb, we cannot use SP + reg, so reject SP. */
2082 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2083 REG_OK_FOR_INDEX_P (X)
2084
2085 #define ARM_BASE_REGISTER_RTX_P(X) \
2086 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
2087
2088 #define ARM_INDEX_REGISTER_RTX_P(X) \
2089 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
2090
2091 /* Specify the machine mode that this machine uses
2092 for the index in the tablejump instruction. */
2093 #define CASE_VECTOR_MODE Pmode
2094
2095 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \
2096 || (TARGET_THUMB1 \
2097 && (optimize_size || flag_pic))) \
2098 && (!target_pure_code))
2099
2100
2101 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2102 (TARGET_THUMB1 \
2103 ? (min >= 0 && max < 512 \
2104 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2105 : min >= -256 && max < 256 \
2106 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2107 : min >= 0 && max < 8192 \
2108 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2109 : min >= -4096 && max < 4096 \
2110 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2111 : SImode) \
2112 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
2113 : (max >= 0x200) ? HImode \
2114 : QImode))
2115
2116 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2117 unsigned is probably best, but may break some code. */
2118 #ifndef DEFAULT_SIGNED_CHAR
2119 #define DEFAULT_SIGNED_CHAR 0
2120 #endif
2121
2122 /* Max number of bytes we can move from memory to memory
2123 in one reasonably fast instruction. */
2124 #define MOVE_MAX 4
2125
2126 #undef MOVE_RATIO
2127 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2128
2129 /* Define if operations between registers always perform the operation
2130 on the full register even if a narrower mode is specified. */
2131 #define WORD_REGISTER_OPERATIONS 1
2132
2133 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2134 will either zero-extend or sign-extend. The value of this macro should
2135 be the code that says which one of the two operations is implicitly
2136 done, UNKNOWN if none. */
2137 #define LOAD_EXTEND_OP(MODE) \
2138 (TARGET_THUMB ? ZERO_EXTEND : \
2139 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2140 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2141
2142 /* Nonzero if access to memory by bytes is slow and undesirable. */
2143 #define SLOW_BYTE_ACCESS 0
2144
2145 /* Immediate shift counts are truncated by the output routines (or was it
2146 the assembler?). Shift counts in a register are truncated by ARM. Note
2147 that the native compiler puts too large (> 32) immediate shift counts
2148 into a register and shifts by the register, letting the ARM decide what
2149 to do instead of doing that itself. */
2150 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2151 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2152 On the arm, Y in a register is used modulo 256 for the shift. Only for
2153 rotates is modulo 32 used. */
2154 /* #define SHIFT_COUNT_TRUNCATED 1 */
2155
2156 /* Calling from registers is a massive pain. */
2157 #define NO_FUNCTION_CSE 1
2158
2159 /* The machine modes of pointers and functions */
2160 #define Pmode SImode
2161 #define FUNCTION_MODE Pmode
2162
2163 #define ARM_FRAME_RTX(X) \
2164 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2165 || (X) == arg_pointer_rtx)
2166
2167 /* Try to generate sequences that don't involve branches, we can then use
2168 conditional instructions. */
2169 #define BRANCH_COST(speed_p, predictable_p) \
2170 ((arm_branch_cost != -1) ? arm_branch_cost : \
2171 (current_tune->branch_cost (speed_p, predictable_p)))
2172
2173 /* False if short circuit operation is preferred. */
2174 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
2175 ((optimize_size) \
2176 ? (TARGET_THUMB ? false : true) \
2177 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \
2178 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm))
2179
2180
2181 /* Position Independent Code. */
2182 /* We decide which register to use based on the compilation options and
2183 the assembler in use; this is more general than the APCS restriction of
2184 using sb (r9) all the time. */
2185 extern unsigned arm_pic_register;
2186
2187 /* The register number of the register used to address a table of static
2188 data addresses in memory. */
2189 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2190
2191 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
2192 entries would need to handle saving and restoring it). */
2193 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
2194
2195 /* We can't directly access anything that contains a symbol,
2196 nor can we indirect via the constant pool. One exception is
2197 UNSPEC_TLS, which is always PIC. */
2198 #define LEGITIMATE_PIC_OPERAND_P(X) \
2199 (!(symbol_mentioned_p (X) \
2200 || label_mentioned_p (X) \
2201 || (GET_CODE (X) == SYMBOL_REF \
2202 && CONSTANT_POOL_ADDRESS_P (X) \
2203 && (symbol_mentioned_p (get_pool_constant (X)) \
2204 || label_mentioned_p (get_pool_constant (X))))) \
2205 || tls_mentioned_p (X))
2206
2207 /* We may want to save the PIC register if it is a dedicated one. */
2208 #define PIC_REGISTER_MAY_NEED_SAVING \
2209 (flag_pic \
2210 && !TARGET_SINGLE_PIC_BASE \
2211 && !TARGET_FDPIC \
2212 && arm_pic_register != INVALID_REGNUM)
2213
2214 /* We need to know when we are making a constant pool; this determines
2215 whether data needs to be in the GOT or can be referenced via a GOT
2216 offset. */
2217 extern int making_const_table;
2218
2219 /* Handle pragmas for compatibility with Intel's compilers. */
2220 /* Also abuse this to register additional C specific EABI attributes. */
2221 #define REGISTER_TARGET_PRAGMAS() do { \
2222 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2223 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2224 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2225 arm_lang_object_attributes_init(); \
2226 arm_register_target_pragmas(); \
2227 } while (0)
2228
2229 /* Condition code information. */
2230 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2231 return the mode to be used for the comparison. */
2232
2233 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2234
2235 #define REVERSIBLE_CC_MODE(MODE) 1
2236
2237 #define REVERSE_CONDITION(CODE,MODE) \
2238 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2239 ? reverse_condition_maybe_unordered (code) \
2240 : reverse_condition (code))
2241
2242 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2243 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
2244 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2245 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
2246
2247 #define CC_STATUS_INIT \
2248 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2249
2250 #undef ASM_APP_ON
2251 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \
2252 "\t.syntax divided\n")
2253
2254 #undef ASM_APP_OFF
2255 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \
2256 "\t.thumb\n\t.syntax unified\n")
2257
2258 /* Output a push or a pop instruction (only used when profiling).
2259 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2260 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2261 that r7 isn't used by the function profiler, so we can use it as a
2262 scratch reg. WARNING: This isn't safe in the general case! It may be
2263 sensitive to future changes in final.cc:profile_function. */
2264 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2265 do \
2266 { \
2267 if (TARGET_THUMB1 \
2268 && (REGNO) == STATIC_CHAIN_REGNUM) \
2269 { \
2270 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2271 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2272 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2273 } \
2274 else \
2275 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2276 } while (0)
2277
2278
2279 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2280 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2281 do \
2282 { \
2283 if (TARGET_THUMB1 \
2284 && (REGNO) == STATIC_CHAIN_REGNUM) \
2285 { \
2286 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2287 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2288 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2289 } \
2290 else \
2291 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2292 } while (0)
2293
2294 #define ADDR_VEC_ALIGN(JUMPTABLE) \
2295 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2296
2297 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2298 default alignment from elfos.h. */
2299 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2300 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
2301
2302 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
2303 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
2304 ? 1 : 0)
2305
2306 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2307 arm_declare_function_name ((STREAM), (NAME), (DECL));
2308
2309 /* For aliases of functions we use .thumb_set instead. */
2310 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2311 do \
2312 { \
2313 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2314 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2315 \
2316 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2317 { \
2318 fprintf (FILE, "\t.thumb_set "); \
2319 assemble_name (FILE, LABEL1); \
2320 fprintf (FILE, ","); \
2321 assemble_name (FILE, LABEL2); \
2322 fprintf (FILE, "\n"); \
2323 } \
2324 else \
2325 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2326 } \
2327 while (0)
2328
2329 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2330 /* To support -falign-* switches we need to use .p2align so
2331 that alignment directives in code sections will be padded
2332 with no-op instructions, rather than zeroes. */
2333 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2334 if ((LOG) != 0) \
2335 { \
2336 if ((MAX_SKIP) == 0) \
2337 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2338 else \
2339 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2340 (int) (LOG), (int) (MAX_SKIP)); \
2341 }
2342 #endif
2343
2344 /* Add two bytes to the length of conditionally executed Thumb-2
2345 instructions for the IT instruction. */
2346 #define ADJUST_INSN_LENGTH(insn, length) \
2347 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2348 length += 2;
2349
2350 /* Only perform branch elimination (by making instructions conditional) if
2351 we're optimizing. For Thumb-2 check if any IT instructions need
2352 outputting. */
2353 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2354 if (TARGET_ARM && optimize) \
2355 arm_final_prescan_insn (INSN); \
2356 else if (TARGET_THUMB2) \
2357 thumb2_final_prescan_insn (INSN); \
2358 else if (TARGET_THUMB1) \
2359 thumb1_final_prescan_insn (INSN)
2360
2361 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2362 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2363 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2364 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2365 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2366 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2367 : 0))))
2368
2369 /* A C expression whose value is RTL representing the value of the return
2370 address for the frame COUNT steps up from the current frame. */
2371
2372 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2373 arm_return_addr (COUNT, FRAME)
2374
2375 /* Mask of the bits in the PC that contain the real return address
2376 when running in 26-bit mode. */
2377 #define RETURN_ADDR_MASK26 (0x03fffffc)
2378
2379 /* Pick up the return address upon entry to a procedure. Used for
2380 dwarf2 unwind information. This also enables the table driven
2381 mechanism. */
2382 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2383 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2384
2385 /* Used to mask out junk bits from the return address, such as
2386 processor state, interrupt status, condition codes and the like. */
2387 #define MASK_RETURN_ADDR \
2388 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2389 in 26 bit mode, the condition codes must be masked out of the \
2390 return address. This does not apply to ARM6 and later processors \
2391 when running in 32 bit mode. */ \
2392 ((arm_arch4 || TARGET_THUMB) \
2393 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2394 : arm_gen_return_addr_mask ())
2395
2396
2397 /* Do not emit .note.GNU-stack by default. */
2398 #ifndef NEED_INDICATE_EXEC_STACK
2399 #define NEED_INDICATE_EXEC_STACK 0
2400 #endif
2401
2402 #define TARGET_ARM_ARCH \
2403 (arm_base_arch) \
2404
2405 /* The highest Thumb instruction set version supported by the chip. */
2406 #define TARGET_ARM_ARCH_ISA_THUMB \
2407 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0))
2408
2409 /* Expands to an upper-case char of the target's architectural
2410 profile. */
2411 #define TARGET_ARM_ARCH_PROFILE \
2412 (arm_active_target.profile)
2413
2414 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2415 Bit 0 for bytes, up to bit 3 for double-words. */
2416 #define TARGET_ARM_FEATURE_LDREX \
2417 ((TARGET_HAVE_LDREX ? 4 : 0) \
2418 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2419 | (TARGET_HAVE_LDREXD ? 8 : 0))
2420
2421 /* Set as a bit mask indicating the available widths of hardware floating
2422 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2423 32-bit support, bit 3 indicates 64-bit support. */
2424 #define TARGET_ARM_FP \
2425 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \
2426 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \
2427 : 0)
2428
2429
2430 /* Set as a bit mask indicating the available widths of floating point
2431 types for hardware NEON floating point. This is the same as
2432 TARGET_ARM_FP without the 64-bit bit set. */
2433 #define TARGET_NEON_FP \
2434 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \
2435 : 0)
2436
2437 /* Name of the automatic fpu-selection option. */
2438 #define FPUTYPE_AUTO "auto"
2439
2440 /* The maximum number of parallel loads or stores we support in an ldm/stm
2441 instruction. */
2442 #define MAX_LDM_STM_OPS 4
2443
2444 extern const char *arm_rewrite_mcpu (int argc, const char **argv);
2445 extern const char *arm_rewrite_march (int argc, const char **argv);
2446 extern const char *arm_asm_auto_mfpu (int argc, const char **argv);
2447 #define ASM_CPU_SPEC_FUNCTIONS \
2448 { "rewrite_mcpu", arm_rewrite_mcpu }, \
2449 { "rewrite_march", arm_rewrite_march }, \
2450 { "asm_auto_mfpu", arm_asm_auto_mfpu },
2451
2452 #define ASM_CPU_SPEC \
2453 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \
2454 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \
2455 " march=*:-march=%:rewrite_march(%{march=*:%*});" \
2456 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \
2457 " }"
2458
2459 extern const char *arm_target_mode (int argc, const char **argv);
2460 #define TARGET_MODE_SPEC_FUNCTIONS \
2461 { "target_mode_check", arm_target_mode },
2462
2463 /* -mcpu=native handling only makes sense with compiler running on
2464 an ARM chip. */
2465 #if defined(__arm__)
2466 extern const char *host_detect_local_cpu (int argc, const char **argv);
2467 #define HAVE_LOCAL_CPU_DETECT
2468 # define MCPU_MTUNE_NATIVE_FUNCTIONS \
2469 { "local_cpu_detect", host_detect_local_cpu },
2470 # define MCPU_MTUNE_NATIVE_SPECS \
2471 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2472 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2473 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2474 #else
2475 # define MCPU_MTUNE_NATIVE_FUNCTIONS
2476 # define MCPU_MTUNE_NATIVE_SPECS ""
2477 #endif
2478
2479 const char *arm_canon_arch_option (int argc, const char **argv);
2480 const char *arm_canon_arch_multilib_option (int argc, const char **argv);
2481
2482 #define CANON_ARCH_SPEC_FUNCTION \
2483 { "canon_arch", arm_canon_arch_option },
2484
2485 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \
2486 { "canon_arch_multilib", arm_canon_arch_multilib_option },
2487
2488 const char *arm_be8_option (int argc, const char **argv);
2489 #define BE8_SPEC_FUNCTION \
2490 { "be8_linkopt", arm_be8_option },
2491
2492 # define EXTRA_SPEC_FUNCTIONS \
2493 MCPU_MTUNE_NATIVE_FUNCTIONS \
2494 ASM_CPU_SPEC_FUNCTIONS \
2495 CANON_ARCH_SPEC_FUNCTION \
2496 CANON_ARCH_MULTILIB_SPEC_FUNCTION \
2497 TARGET_MODE_SPEC_FUNCTIONS \
2498 BE8_SPEC_FUNCTION
2499
2500 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified
2501 via the configuration option --with-mode or via the command line. The
2502 function target_mode_check is called to do the check with either:
2503 - an array of -march values if any is given;
2504 - an array of -mcpu values if any is given;
2505 - an empty array. */
2506 #define TARGET_MODE_SPECS \
2507 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}"
2508
2509 /* Generate a canonical string to represent the architecture selected. */
2510 #define ARCH_CANONICAL_SPECS \
2511 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \
2512 " %{march=*: arch %*} " \
2513 " %{mfpu=*: fpu %*} " \
2514 " %{mfloat-abi=*: abi %*}" \
2515 " %<march=*) "
2516
2517 /* Generate a canonical string to represent the architecture selected ignoring
2518 the options not required for multilib linking. */
2519 #define MULTILIB_ARCH_CANONICAL_SPECS \
2520 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \
2521 " %{march=*: arch %*} " \
2522 " %{mfpu=*: fpu %*} " \
2523 " %{mfloat-abi=*: abi %*}" \
2524 " %<mlibarch=*) "
2525
2526 /* Complete set of specs for the driver. Commas separate the
2527 individual rules so that any option suppression (%<opt...)is
2528 completed before starting subsequent rules. */
2529 #define DRIVER_SELF_SPECS \
2530 MCPU_MTUNE_NATIVE_SPECS, \
2531 TARGET_MODE_SPECS, \
2532 MULTILIB_ARCH_CANONICAL_SPECS, \
2533 ARCH_CANONICAL_SPECS
2534
2535 #define TARGET_SUPPORTS_WIDE_INT 1
2536
2537 /* For switching between functions with different target attributes. */
2538 #define SWITCHABLE_TARGET 1
2539
2540 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute
2541 representation for SHF_ARM_PURECODE in GCC. */
2542 #define SECTION_ARM_PURECODE SECTION_MACH_DEP
2543
2544 #endif /* ! GCC_ARM_H */