1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2023 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22 #ifndef GCC_AARCH64_H
23 #define GCC_AARCH64_H
24
25 /* Make these flags read-only so that all uses go via
26 aarch64_set_asm_isa_flags. */
27 #ifndef GENERATOR_FILE
28 #undef aarch64_asm_isa_flags
29 #define aarch64_asm_isa_flags \
30 ((aarch64_feature_flags) global_options.x_aarch64_asm_isa_flags)
31 #undef aarch64_isa_flags
32 #define aarch64_isa_flags \
33 ((aarch64_feature_flags) global_options.x_aarch64_isa_flags)
34 #endif
35
36 /* Target CPU builtins. */
37 #define TARGET_CPU_CPP_BUILTINS() \
38 aarch64_cpu_cpp_builtins (pfile)
39
40
41
42 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
43
44 /* Target machine storage layout. */
45
46 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
47 if (GET_MODE_CLASS (MODE) == MODE_INT \
48 && GET_MODE_SIZE (MODE) < 4) \
49 { \
50 if (MODE == QImode || MODE == HImode) \
51 { \
52 MODE = SImode; \
53 } \
54 }
55
56 /* Bits are always numbered from the LSBit. */
57 #define BITS_BIG_ENDIAN 0
58
59 /* Big/little-endian flavour. */
60 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
61 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
62
63 /* AdvSIMD is supported in the default configuration, unless disabled by
64 -mgeneral-regs-only or by the +nosimd extension. */
65 #define TARGET_SIMD (AARCH64_ISA_SIMD)
66 #define TARGET_FLOAT (AARCH64_ISA_FP)
67
68 #define UNITS_PER_WORD 8
69
70 #define UNITS_PER_VREG 16
71
72 #define PARM_BOUNDARY 64
73
74 #define STACK_BOUNDARY 128
75
76 #define FUNCTION_BOUNDARY 32
77
78 #define EMPTY_FIELD_BOUNDARY 32
79
80 #define BIGGEST_ALIGNMENT 128
81
82 #define SHORT_TYPE_SIZE 16
83
84 #define INT_TYPE_SIZE 32
85
86 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
87
88 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
89
90 #define LONG_LONG_TYPE_SIZE 64
91
92 #define FLOAT_TYPE_SIZE 32
93
94 #define DOUBLE_TYPE_SIZE 64
95
96 #define LONG_DOUBLE_TYPE_SIZE 128
97
98 /* This value is the amount of bytes a caller is allowed to drop the stack
99 before probing has to be done for stack clash protection. */
100 #define STACK_CLASH_CALLER_GUARD 1024
101
102 /* This value represents the minimum amount of bytes we expect the function's
103 outgoing arguments to be when stack-clash is enabled. */
104 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
105
106 /* This value controls how many pages we manually unroll the loop for when
107 generating stack clash probes. */
108 #define STACK_CLASH_MAX_UNROLL_PAGES 4
109
110 /* The architecture reserves all bits of the address for hardware use,
111 so the vbit must go into the delta field of pointers to member
112 functions. This is the same config as that in the AArch32
113 port. */
114 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
115
116
117 /* Emit calls to libgcc helpers for atomic operations for runtime detection
118 of LSE instructions. */
119 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics)
120
121 /* Align definitions of arrays, unions and structures so that
122 initializations and copies can be made more efficient. This is not
123 ABI-changing, so it only affects places where we can see the
124 definition. Increasing the alignment tends to introduce padding,
125 so don't do this when optimizing for size/conserving stack space. */
126 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
127 (((COND) && ((ALIGN) < BITS_PER_WORD) \
128 && (TREE_CODE (EXP) == ARRAY_TYPE \
129 || TREE_CODE (EXP) == UNION_TYPE \
130 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
131
132 /* Align global data. */
133 #define DATA_ALIGNMENT(EXP, ALIGN) \
134 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
135
136 /* Similarly, make sure that objects on the stack are sensibly aligned. */
137 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
138 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
139
140 #define STRUCTURE_SIZE_BOUNDARY 8
141
142 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */
143 #define MALLOC_ABI_ALIGNMENT 128
144
145 /* Defined by the ABI */
146 #define WCHAR_TYPE "unsigned int"
147 #define WCHAR_TYPE_SIZE 32
148
149 /* Using long long breaks -ansi and -std=c90, so these will need to be
150 made conditional for an LLP64 ABI. */
151
152 #define SIZE_TYPE "long unsigned int"
153
154 #define PTRDIFF_TYPE "long int"
155
156 #define PCC_BITFIELD_TYPE_MATTERS 1
157
158 #ifndef USED_FOR_TARGET
159
160 /* Define an enum of all features (architectures and extensions). */
161 enum class aarch64_feature : unsigned char {
162 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) IDENT,
163 #define AARCH64_ARCH(A, B, IDENT, D, E) IDENT,
164 #include "aarch64-option-extensions.def"
165 #include "aarch64-arches.def"
166 };
167
168 /* Define unique flags for each of the above. */
169 #define HANDLE(IDENT) \
170 constexpr auto AARCH64_FL_##IDENT \
171 = aarch64_feature_flags (1) << int (aarch64_feature::IDENT);
172 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT)
173 #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT)
174 #include "aarch64-option-extensions.def"
175 #include "aarch64-arches.def"
176 #undef HANDLE
177
178 #endif
179
180 /* Macros to test ISA flags. */
181
182 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC)
183 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO)
184 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP)
185 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD)
186 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE)
187 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA)
188 #define AARCH64_ISA_V8_2A (aarch64_isa_flags & AARCH64_FL_V8_2A)
189 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16)
190 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE)
191 #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2)
192 #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES)
193 #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
194 #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
195 #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
196 #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A)
197 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD)
198 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES)
199 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2)
200 #define AARCH64_ISA_V8_4A (aarch64_isa_flags & AARCH64_FL_V8_4A)
201 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4)
202 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3)
203 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML)
204 #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC)
205 #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_V8_4A)
206 #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG)
207 #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A)
208 #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)
209 #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG)
210 #define AARCH64_ISA_V8_6A (aarch64_isa_flags & AARCH64_FL_V8_6A)
211 #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM)
212 #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM)
213 #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM)
214 #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16)
215 #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB)
216 #define AARCH64_ISA_V8R (aarch64_isa_flags & AARCH64_FL_V8R)
217 #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH)
218 #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A)
219 #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A)
220 #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A)
221 #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A)
222 #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS)
223 #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64)
224 #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
225 #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC)
226
227 /* Crypto is an optional extension to AdvSIMD. */
228 #define TARGET_CRYPTO (AARCH64_ISA_CRYPTO)
229
230 /* SHA2 is an optional extension to AdvSIMD. */
231 #define TARGET_SHA2 (AARCH64_ISA_SHA2)
232
233 /* SHA3 is an optional extension to AdvSIMD. */
234 #define TARGET_SHA3 (AARCH64_ISA_SHA3)
235
236 /* AES is an optional extension to AdvSIMD. */
237 #define TARGET_AES (AARCH64_ISA_AES)
238
239 /* SM is an optional extension to AdvSIMD. */
240 #define TARGET_SM4 (AARCH64_ISA_SM4)
241
242 /* FP16FML is an optional extension to AdvSIMD. */
243 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
244
245 /* CRC instructions that can be enabled through +crc arch extension. */
246 #define TARGET_CRC32 (AARCH64_ISA_CRC)
247
248 /* Atomic instructions that can be enabled through the +lse extension. */
249 #define TARGET_LSE (AARCH64_ISA_LSE)
250
251 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */
252 #define TARGET_FP_F16INST (AARCH64_ISA_F16)
253 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
254
255 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */
256 #define TARGET_DOTPROD (AARCH64_ISA_DOTPROD)
257
258 /* SVE instructions, enabled through +sve. */
259 #define TARGET_SVE (AARCH64_ISA_SVE)
260
261 /* SVE2 instructions, enabled through +sve2. */
262 #define TARGET_SVE2 (AARCH64_ISA_SVE2)
263
264 /* SVE2 AES instructions, enabled through +sve2-aes. */
265 #define TARGET_SVE2_AES (AARCH64_ISA_SVE2_AES)
266
267 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */
268 #define TARGET_SVE2_BITPERM (AARCH64_ISA_SVE2_BITPERM)
269
270 /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */
271 #define TARGET_SVE2_SHA3 (AARCH64_ISA_SVE2_SHA3)
272
273 /* SVE2 SM4 instructions, enabled through +sve2-sm4. */
274 #define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4)
275
276 /* ARMv8.3-A features. */
277 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A)
278
279 /* Javascript conversion instruction from Armv8.3-a. */
280 #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3A)
281
282 /* Armv8.3-a Complex number extension to AdvSIMD extensions. */
283 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
284
285 /* Floating-point rounding instructions from Armv8.5-a. */
286 #define TARGET_FRINT (AARCH64_ISA_V8_5A && TARGET_FLOAT)
287
288 /* TME instructions are enabled. */
289 #define TARGET_TME (AARCH64_ISA_TME)
290
291 /* Random number instructions from Armv8.5-a. */
292 #define TARGET_RNG (AARCH64_ISA_RNG)
293
294 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
295 #define TARGET_MEMTAG (AARCH64_ISA_MEMTAG)
296
297 /* I8MM instructions are enabled through +i8mm. */
298 #define TARGET_I8MM (AARCH64_ISA_I8MM)
299 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM)
300
301 /* F32MM instructions are enabled through +f32mm. */
302 #define TARGET_SVE_F32MM (AARCH64_ISA_F32MM)
303
304 /* F64MM instructions are enabled through +f64mm. */
305 #define TARGET_SVE_F64MM (AARCH64_ISA_F64MM)
306
307 /* BF16 instructions are enabled through +bf16. */
308 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
309 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
310 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16)
311
312 /* PAUTH instructions are enabled through +pauth. */
313 #define TARGET_PAUTH (AARCH64_ISA_PAUTH)
314
315 /* BTI instructions exist from Armv8.5-a onwards. Their automatic use is
316 enabled through -mbranch-protection by using NOP-space instructions,
317 but this TARGET_ is used for defining BTI-related ACLE things. */
318 #define TARGET_BTI (AARCH64_ISA_V8_5A)
319
320 /* MOPS instructions are enabled through +mops. */
321 #define TARGET_MOPS (AARCH64_ISA_MOPS)
322
323 /* LS64 instructions are enabled through +ls64. */
324 #define TARGET_LS64 (AARCH64_ISA_LS64)
325
326 /* CSSC instructions are enabled through +cssc. */
327 #define TARGET_CSSC (AARCH64_ISA_CSSC)
328
329 /* Make sure this is always defined so we don't have to check for ifdefs
330 but rather use normal ifs. */
331 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
332 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
333 #else
334 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
335 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
336 #endif
337
338 /* SB instruction is enabled through +sb. */
339 #define TARGET_SB (AARCH64_ISA_SB)
340
341 /* RCPC loads from Armv8.3-a. */
342 #define TARGET_RCPC (AARCH64_ISA_RCPC)
343
344 /* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR
345 and sign-extending versions.*/
346 #define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4)
347
348 /* Apply the workaround for Cortex-A53 erratum 835769. */
349 #define TARGET_FIX_ERR_A53_835769 \
350 ((aarch64_fix_a53_err835769 == 2) \
351 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
352
353 /* Make sure this is always defined so we don't have to check for ifdefs
354 but rather use normal ifs. */
355 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
356 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
357 #else
358 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
359 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
360 #endif
361
362 /* Apply the workaround for Cortex-A53 erratum 843419. */
363 #define TARGET_FIX_ERR_A53_843419 \
364 ((aarch64_fix_a53_err843419 == 2) \
365 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
366
367 /* ARMv8.1-A Adv.SIMD support. */
368 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
369
370 /* Standard register usage. */
371
372 /* 31 64-bit general purpose registers R0-R30:
373 R30 LR (link register)
374 R29 FP (frame pointer)
375 R19-R28 Callee-saved registers
376 R18 The platform register; use as temporary register.
377 R17 IP1 The second intra-procedure-call temporary register
378 (can be used by call veneers and PLT code); otherwise use
379 as a temporary register
380 R16 IP0 The first intra-procedure-call temporary register (can
381 be used by call veneers and PLT code); otherwise use as a
382 temporary register
383 R9-R15 Temporary registers
384 R8 Structure value parameter / temporary register
385 R0-R7 Parameter/result registers
386
387 SP stack pointer, encoded as X/R31 where permitted.
388 ZR zero register, encoded as X/R31 elsewhere
389
390 32 x 128-bit floating-point/vector registers
391 V16-V31 Caller-saved (temporary) registers
392 V8-V15 Callee-saved registers
393 V0-V7 Parameter/result registers
394
395 The vector register V0 holds scalar B0, H0, S0 and D0 in its least
396 significant bits. Unlike AArch32 S1 is not packed into D0, etc.
397
398 P0-P7 Predicate low registers: valid in all predicate contexts
399 P8-P15 Predicate high registers: used as scratch space
400
401 FFR First Fault Register, a fixed-use SVE predicate register
402 FFRT FFR token: a fake register used for modelling dependencies
403
404 VG Pseudo "vector granules" register
405
406 VG is the number of 64-bit elements in an SVE vector. We define
407 it as a hard register so that we can easily map it to the DWARF VG
408 register. GCC internally uses the poly_int variable aarch64_sve_vg
409 instead. */
410
411 #define FIXED_REGISTERS \
412 { \
413 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \
414 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \
415 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \
416 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \
417 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \
418 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
419 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \
420 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \
421 1, 1, 1, 1, /* SFP, AP, CC, VG */ \
422 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \
423 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \
424 1, 1 /* FFR and FFRT */ \
425 }
426
427 /* X30 is marked as caller-saved which is in line with regular function call
428 behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does
429 that for regular function calls and avoids it for sibcalls. X30 is
430 considered live for sibcalls; EPILOGUE_USES helps achieve that by returning
431 true but not until function epilogues have been generated. This ensures
432 that X30 is available for use in leaf functions if needed. */
433
434 #define CALL_USED_REGISTERS \
435 { \
436 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \
437 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \
438 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \
439 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \
440 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \
441 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \
442 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \
443 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \
444 1, 1, 1, 1, /* SFP, AP, CC, VG */ \
445 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \
446 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \
447 1, 1 /* FFR and FFRT */ \
448 }
449
450 #define REGISTER_NAMES \
451 { \
452 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \
453 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \
454 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \
455 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \
456 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
457 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
458 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
459 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
460 "sfp", "ap", "cc", "vg", \
461 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \
462 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \
463 "ffr", "ffrt" \
464 }
465
466 /* Generate the register aliases for core register N */
467 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
468 {"w" # N, R0_REGNUM + (N)}
469
470 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
471 {"d" # N, V0_REGNUM + (N)}, \
472 {"s" # N, V0_REGNUM + (N)}, \
473 {"h" # N, V0_REGNUM + (N)}, \
474 {"b" # N, V0_REGNUM + (N)}, \
475 {"z" # N, V0_REGNUM + (N)}
476
477 /* Provide aliases for all of the ISA defined register name forms.
478 These aliases are convenient for use in the clobber lists of inline
479 asm statements. */
480
481 #define ADDITIONAL_REGISTER_NAMES \
482 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \
483 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \
484 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \
485 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
486 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
487 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
488 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
489 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
490 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \
491 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \
492 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \
493 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
494 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
495 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
496 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
497 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
498 }
499
500 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
501
502 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
503 the stack pointer does not matter. This is only true if the function
504 uses alloca. */
505 #define EXIT_IGNORE_STACK (cfun->calls_alloca)
506
507 #define STATIC_CHAIN_REGNUM R18_REGNUM
508 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM
509 #define FRAME_POINTER_REGNUM SFP_REGNUM
510 #define STACK_POINTER_REGNUM SP_REGNUM
511 #define ARG_POINTER_REGNUM AP_REGNUM
512 #define FIRST_PSEUDO_REGISTER (FFRT_REGNUM + 1)
513
514 /* The number of argument registers available for each class. */
515 #define NUM_ARG_REGS 8
516 #define NUM_FP_ARG_REGS 8
517 #define NUM_PR_ARG_REGS 4
518
519 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
520 four members. */
521 #define HA_MAX_NUM_FLDS 4
522
523 /* External dwarf register number scheme. These number are used to
524 identify registers in dwarf debug information, the values are
525 defined by the AArch64 ABI. The numbering scheme is independent of
526 GCC's internal register numbering scheme. */
527
528 #define AARCH64_DWARF_R0 0
529
530 /* The number of R registers, note 31! not 32. */
531 #define AARCH64_DWARF_NUMBER_R 31
532
533 #define AARCH64_DWARF_SP 31
534 #define AARCH64_DWARF_VG 46
535 #define AARCH64_DWARF_P0 48
536 #define AARCH64_DWARF_V0 64
537
538 /* The number of V registers. */
539 #define AARCH64_DWARF_NUMBER_V 32
540
541 /* For signal frames we need to use an alternative return column. This
542 value must not correspond to a hard register and must be out of the
543 range of DWARF_FRAME_REGNUM(). */
544 #define DWARF_ALT_FRAME_RETURN_COLUMN \
545 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
546
547 /* We add 1 extra frame register for use as the
548 DWARF_ALT_FRAME_RETURN_COLUMN. */
549 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
550
551
552 #define DEBUGGER_REGNO(REGNO) aarch64_debugger_regno (REGNO)
553 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
554 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same
555 as the default definition in dwarf2out.cc. */
556 #undef DWARF_FRAME_REGNUM
557 #define DWARF_FRAME_REGNUM(REGNO) DEBUGGER_REGNO (REGNO)
558
559 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
560
561 #define DWARF2_UNWIND_INFO 1
562
563 /* Use R0 through R3 to pass exception handling information. */
564 #define EH_RETURN_DATA_REGNO(N) \
565 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
566
567 /* Select a format to encode pointers in exception handling data. */
568 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
569 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
570
571 /* Output the assembly strings we want to add to a function definition. */
572 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \
573 aarch64_declare_function_name (STR, NAME, DECL)
574
575 /* Output assembly strings for alias definition. */
576 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \
577 aarch64_asm_output_alias (STR, DECL, TARGET)
578
579 /* Output assembly strings for undefined extern symbols. */
580 #undef ASM_OUTPUT_EXTERNAL
581 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \
582 aarch64_asm_output_external (STR, DECL, NAME)
583
584 /* Output assembly strings after .cfi_startproc is emitted. */
585 #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
586
587 /* For EH returns X4 contains the stack adjustment. */
588 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM)
589 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx ()
590
591 #undef TARGET_COMPUTE_FRAME_LAYOUT
592 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame
593
594 /* Register in which the structure value is to be returned. */
595 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
596
597 /* Non-zero if REGNO is part of the Core register set.
598
599 The rather unusual way of expressing this check is to avoid
600 warnings when building the compiler when R0_REGNUM is 0 and REGNO
601 is unsigned. */
602 #define GP_REGNUM_P(REGNO) \
603 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
604
605 /* Registers known to be preserved over a BL instruction. This consists of the
606 GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the
607 BL instruction itself, while the x16 and x17 registers may be used by
608 veneers which can be inserted by the linker. */
609 #define STUB_REGNUM_P(REGNO) \
610 (GP_REGNUM_P (REGNO) \
611 && (REGNO) != R16_REGNUM \
612 && (REGNO) != R17_REGNUM \
613 && (REGNO) != R30_REGNUM) \
614
615 #define FP_REGNUM_P(REGNO) \
616 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
617
618 #define FP_LO_REGNUM_P(REGNO) \
619 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
620
621 #define FP_LO8_REGNUM_P(REGNO) \
622 (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM))
623
624 #define PR_REGNUM_P(REGNO)\
625 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
626
627 #define PR_LO_REGNUM_P(REGNO)\
628 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
629
630 #define FP_SIMD_SAVED_REGNUM_P(REGNO) \
631 (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
632
633 /* Register and constant classes. */
634
635 enum reg_class
636 {
637 NO_REGS,
638 TAILCALL_ADDR_REGS,
639 STUB_REGS,
640 GENERAL_REGS,
641 STACK_REG,
642 POINTER_REGS,
643 FP_LO8_REGS,
644 FP_LO_REGS,
645 FP_REGS,
646 POINTER_AND_FP_REGS,
647 PR_LO_REGS,
648 PR_HI_REGS,
649 PR_REGS,
650 FFR_REGS,
651 PR_AND_FFR_REGS,
652 ALL_REGS,
653 LIM_REG_CLASSES /* Last */
654 };
655
656 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
657
658 #define REG_CLASS_NAMES \
659 { \
660 "NO_REGS", \
661 "TAILCALL_ADDR_REGS", \
662 "STUB_REGS", \
663 "GENERAL_REGS", \
664 "STACK_REG", \
665 "POINTER_REGS", \
666 "FP_LO8_REGS", \
667 "FP_LO_REGS", \
668 "FP_REGS", \
669 "POINTER_AND_FP_REGS", \
670 "PR_LO_REGS", \
671 "PR_HI_REGS", \
672 "PR_REGS", \
673 "FFR_REGS", \
674 "PR_AND_FFR_REGS", \
675 "ALL_REGS" \
676 }
677
678 #define REG_CLASS_CONTENTS \
679 { \
680 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
681 { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\
682 { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \
683 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
684 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
685 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \
686 { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \
687 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \
688 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
689 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\
690 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \
691 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \
692 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \
693 { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \
694 { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \
695 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \
696 }
697
698 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO)
699
700 #define INDEX_REG_CLASS GENERAL_REGS
701 #define BASE_REG_CLASS POINTER_REGS
702
703 /* Register pairs used to eliminate unneeded registers that point into
704 the stack frame. */
705 #define ELIMINABLE_REGS \
706 { \
707 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
708 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
709 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
710 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
711 }
712
713 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
714 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
715
716 /* CPU/ARCH option handling. */
717 #include "config/aarch64/aarch64-opts.h"
718
719 enum target_cpus
720 {
721 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
722 TARGET_CPU_##INTERNAL_IDENT,
723 #include "aarch64-cores.def"
724 TARGET_CPU_generic
725 };
726
727 /* If there is no CPU defined at configure, use generic as default. */
728 #ifndef TARGET_CPU_DEFAULT
729 # define TARGET_CPU_DEFAULT TARGET_CPU_generic
730 #endif
731
732 /* If inserting NOP before a mult-accumulate insn remember to adjust the
733 length so that conditional branching code is updated appropriately. */
734 #define ADJUST_INSN_LENGTH(insn, length) \
735 do \
736 { \
737 if (aarch64_madd_needs_nop (insn)) \
738 length += 4; \
739 } while (0)
740
741 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
742 aarch64_final_prescan_insn (INSN); \
743
744 /* The processor for which instructions should be scheduled. */
745 extern enum aarch64_processor aarch64_tune;
746
747 /* RTL generation support. */
748 #define INIT_EXPANDERS aarch64_init_expanders ()
749
750
751 /* Stack layout; function entry, exit and calling. */
752 #define STACK_GROWS_DOWNWARD 1
753
754 #define FRAME_GROWS_DOWNWARD 1
755
756 #define ACCUMULATE_OUTGOING_ARGS 1
757
758 #define FIRST_PARM_OFFSET(FNDECL) 0
759
760 /* Fix for VFP */
761 #define LIBCALL_VALUE(MODE) \
762 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
763
764 #define DEFAULT_PCC_STRUCT_RETURN 0
765
766 #ifdef HAVE_POLY_INT_H
767 struct GTY (()) aarch64_frame
768 {
769 poly_int64 reg_offset[LAST_SAVED_REGNUM + 1];
770
771 /* The number of extra stack bytes taken up by register varargs.
772 This area is allocated by the callee at the very top of the
773 frame. This value is rounded up to a multiple of
774 STACK_BOUNDARY. */
775 HOST_WIDE_INT saved_varargs_size;
776
777 /* The size of the callee-save registers with a slot in REG_OFFSET. */
778 poly_int64 saved_regs_size;
779
780 /* The size of the callee-save registers with a slot in REG_OFFSET that
781 are saved below the hard frame pointer. */
782 poly_int64 below_hard_fp_saved_regs_size;
783
784 /* Offset from the base of the frame (incomming SP) to the
785 top of the locals area. This value is always a multiple of
786 STACK_BOUNDARY. */
787 poly_int64 locals_offset;
788
789 /* Offset from the base of the frame (incomming SP) to the
790 hard_frame_pointer. This value is always a multiple of
791 STACK_BOUNDARY. */
792 poly_int64 hard_fp_offset;
793
794 /* The size of the frame. This value is the offset from base of the
795 frame (incomming SP) to the stack_pointer. This value is always
796 a multiple of STACK_BOUNDARY. */
797 poly_int64 frame_size;
798
799 /* The size of the initial stack adjustment before saving callee-saves. */
800 poly_int64 initial_adjust;
801
802 /* The writeback value when pushing callee-save registers.
803 It is zero when no push is used. */
804 HOST_WIDE_INT callee_adjust;
805
806 /* The offset from SP to the callee-save registers after initial_adjust.
807 It may be non-zero if no push is used (ie. callee_adjust == 0). */
808 poly_int64 callee_offset;
809
810 /* The size of the stack adjustment before saving or after restoring
811 SVE registers. */
812 poly_int64 sve_callee_adjust;
813
814 /* The size of the stack adjustment after saving callee-saves. */
815 poly_int64 final_adjust;
816
817 /* Store FP,LR and setup a frame pointer. */
818 bool emit_frame_chain;
819
820 /* In each frame, we can associate up to two register saves with the
821 initial stack allocation. This happens in one of two ways:
822
823 (1) Using an STR or STP with writeback to perform the initial
824 stack allocation. When EMIT_FRAME_CHAIN, the registers will
825 be those needed to create a frame chain.
826
827 Indicated by CALLEE_ADJUST != 0.
828
829 (2) Using a separate STP to set up the frame record, after the
830 initial stack allocation but before setting up the frame pointer.
831 This is used if the offset is too large to use writeback.
832
833 Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN.
834
835 These fields indicate which registers we've decided to handle using
836 (1) or (2), or INVALID_REGNUM if none.
837
838 In some cases we don't always need to pop all registers in the push
839 candidates, pop candidates record which registers need to be popped
840 eventually. The initial value of a pop candidate is copied from its
841 corresponding push candidate.
842
843 Currently, different pop candidates are only used for shadow call
844 stack. When "-fsanitize=shadow-call-stack" is specified, we replace
845 x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is
846 not popped twice. */
847 unsigned wb_push_candidate1;
848 unsigned wb_push_candidate2;
849 unsigned wb_pop_candidate1;
850 unsigned wb_pop_candidate2;
851
852 /* Big-endian SVE frames need a spare predicate register in order
853 to save vector registers in the correct layout for unwinding.
854 This is the register they should use. */
855 unsigned spare_pred_reg;
856
857 bool laid_out;
858
859 /* True if shadow call stack should be enabled for the current function. */
860 bool is_scs_enabled;
861 };
862
863 #ifdef hash_set_h
864 typedef struct GTY (()) machine_function
865 {
866 struct aarch64_frame frame;
867 /* One entry for each hard register. */
868 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
869 /* One entry for each general purpose register. */
870 rtx call_via[SP_REGNUM];
871 bool label_is_assembled;
872 /* A set of all decls that have been passed to a vld1 intrinsic in the
873 current function. This is used to help guide the vector cost model. */
874 hash_set<tree> *vector_load_decls;
875 } machine_function;
876 #endif
877 #endif
878
879 /* Which ABI to use. */
880 enum aarch64_abi_type
881 {
882 AARCH64_ABI_LP64 = 0,
883 AARCH64_ABI_ILP32 = 1
884 };
885
886 #ifndef AARCH64_ABI_DEFAULT
887 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
888 #endif
889
890 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32)
891
892 enum arm_pcs
893 {
894 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */
895 ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */
896 ARM_PCS_SVE, /* For functions that pass or return
897 values in SVE registers. */
898 ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */
899 ARM_PCS_UNKNOWN
900 };
901
902
903
904
905 /* We can't use machine_mode inside a generator file because it
906 hasn't been created yet; we shouldn't be using any code that
907 needs the real definition though, so this ought to be safe. */
908 #ifdef GENERATOR_FILE
909 #define MACHMODE int
910 #else
911 #include "insn-modes.h"
912 #define MACHMODE machine_mode
913 #endif
914
915 #ifndef USED_FOR_TARGET
916 /* AAPCS related state tracking. */
917 typedef struct
918 {
919 enum arm_pcs pcs_variant;
920 int aapcs_arg_processed; /* No need to lay out this argument again. */
921 int aapcs_ncrn; /* Next Core register number. */
922 int aapcs_nextncrn; /* Next next core register number. */
923 int aapcs_nvrn; /* Next Vector register number. */
924 int aapcs_nextnvrn; /* Next Next Vector register number. */
925 int aapcs_nprn; /* Next Predicate register number. */
926 int aapcs_nextnprn; /* Next Next Predicate register number. */
927 rtx aapcs_reg; /* Register assigned to this argument. This
928 is NULL_RTX if this parameter goes on
929 the stack. */
930 MACHMODE aapcs_vfp_rmode;
931 int aapcs_stack_words; /* If the argument is passed on the stack, this
932 is the number of words needed, after rounding
933 up. Only meaningful when
934 aapcs_reg == NULL_RTX. */
935 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the
936 stack arg area so far. */
937 bool silent_p; /* True if we should act silently, rather than
938 raise an error for invalid calls. */
939 } CUMULATIVE_ARGS;
940 #endif
941
942 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
943 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
944
945 #define PAD_VARARGS_DOWN 0
946
947 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
948 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
949
950 #define FUNCTION_ARG_REGNO_P(REGNO) \
951 aarch64_function_arg_regno_p(REGNO)
952
953
954 /* ISA Features. */
955
956 /* Addressing modes, etc. */
957 #define HAVE_POST_INCREMENT 1
958 #define HAVE_PRE_INCREMENT 1
959 #define HAVE_POST_DECREMENT 1
960 #define HAVE_PRE_DECREMENT 1
961 #define HAVE_POST_MODIFY_DISP 1
962 #define HAVE_PRE_MODIFY_DISP 1
963
964 #define MAX_REGS_PER_ADDRESS 2
965
966 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X)
967
968 #define REGNO_OK_FOR_BASE_P(REGNO) \
969 aarch64_regno_ok_for_base_p (REGNO, true)
970
971 #define REGNO_OK_FOR_INDEX_P(REGNO) \
972 aarch64_regno_ok_for_index_p (REGNO, true)
973
974 #define LEGITIMATE_PIC_OPERAND_P(X) \
975 aarch64_legitimate_pic_operand_p (X)
976
977 #define CASE_VECTOR_MODE Pmode
978
979 #define DEFAULT_SIGNED_CHAR 0
980
981 /* An integer expression for the size in bits of the largest integer machine
982 mode that should actually be used. We allow pairs of registers. */
983 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
984
985 /* Maximum bytes moved by a single instruction (load/store pair). */
986 #define MOVE_MAX (UNITS_PER_WORD * 2)
987
988 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */
989 #define AARCH64_CALL_RATIO 8
990
991 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
992 move_by_pieces will continually copy the largest safe chunks. So a
993 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient
994 for both size and speed of copy, so we will instead use the "cpymem"
995 standard name to implement the copy. This logic does not apply when
996 targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in
997 that case. */
998 #define MOVE_RATIO(speed) \
999 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
1000
1001 /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when
1002 we would use more than 3 scalar instructions.
1003 Otherwise follow a sensible default: when optimizing for size, give a better
1004 estimate of the length of a memset call, but use the default otherwise. */
1005 #define CLEAR_RATIO(speed) \
1006 (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO)
1007
1008 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without
1009 -mstrict-align, make decisions in "setmem". Otherwise follow a sensible
1010 default: when optimizing for size adjust the ratio to account for the
1011 overhead of loading the constant. */
1012 #define SET_RATIO(speed) \
1013 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2)
1014
1015 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is
1016 rarely a good idea in straight-line code since it adds an extra address
1017 dependency between each instruction. Better to use incrementing offsets. */
1018 #define USE_LOAD_POST_INCREMENT(MODE) 0
1019 #define USE_LOAD_POST_DECREMENT(MODE) 0
1020 #define USE_LOAD_PRE_INCREMENT(MODE) 0
1021 #define USE_LOAD_PRE_DECREMENT(MODE) 0
1022 #define USE_STORE_POST_INCREMENT(MODE) 0
1023 #define USE_STORE_POST_DECREMENT(MODE) 0
1024 #define USE_STORE_PRE_INCREMENT(MODE) 0
1025 #define USE_STORE_PRE_DECREMENT(MODE) 0
1026
1027 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
1028 The assigned word_mode is DImode but operations narrower than SImode
1029 behave as 32-bit operations if using the W-form of the registers rather
1030 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
1031 expects. */
1032 #define WORD_REGISTER_OPERATIONS 0
1033
1034 /* Define if loading from memory in MODE, an integral mode narrower than
1035 BITS_PER_WORD will either zero-extend or sign-extend. The value of this
1036 macro should be the code that says which one of the two operations is
1037 implicitly done, or UNKNOWN if none. */
1038 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1039
1040 /* Define this macro to be non-zero if instructions will fail to work
1041 if given data not on the nominal alignment. */
1042 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
1043
1044 /* Enable wide bitfield accesses for more efficient bitfield code. */
1045 #define SLOW_BYTE_ACCESS 1
1046
1047 #define NO_FUNCTION_CSE 1
1048
1049 /* Specify the machine mode that the hardware addresses have.
1050 After generation of rtl, the compiler makes no further distinction
1051 between pointers and any other objects of this machine mode. */
1052 #define Pmode DImode
1053
1054 /* A C expression whose value is zero if pointers that need to be extended
1055 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1056 greater then zero if they are zero-extended and less then zero if the
1057 ptr_extend instruction should be used. */
1058 #define POINTERS_EXTEND_UNSIGNED 1
1059
1060 /* Mode of a function address in a call instruction (for indexing purposes). */
1061 #define FUNCTION_MODE Pmode
1062
1063 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y)
1064
1065 /* Having an integer comparison mode guarantees that we can use
1066 reverse_condition, but the usual restrictions apply to floating-point
1067 comparisons. */
1068 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode)
1069
1070 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1071 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1072 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1073 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1074
1075 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
1076
1077 #define RETURN_ADDR_RTX aarch64_return_addr
1078
1079 /* BTI c + 3 insns
1080 + sls barrier of DSB + ISB.
1081 + 2 pointer-sized entries. */
1082 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16))
1083
1084 /* Trampolines contain dwords, so must be dword aligned. */
1085 #define TRAMPOLINE_ALIGNMENT 64
1086
1087 /* Put trampolines in the text section so that mapping symbols work
1088 correctly. */
1089 #define TRAMPOLINE_SECTION text_section
1090
1091 /* To start with. */
1092 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
1093 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
1094
1095
1096 /* Assembly output. */
1097
1098 /* For now we'll make all jump tables pc-relative. */
1099 #define CASE_VECTOR_PC_RELATIVE 1
1100
1101 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1102 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \
1103 : (min < -0x1f0 || max > 0x1f0) ? HImode \
1104 : QImode)
1105
1106 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
1107 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
1108
1109 #define MCOUNT_NAME "_mcount"
1110
1111 #define NO_PROFILE_COUNTERS 1
1112
1113 /* Emit rtl for profiling. Output assembler code to FILE
1114 to call "_mcount" for profiling a function entry. */
1115 #define PROFILE_HOOK(LABEL) \
1116 { \
1117 rtx fun, lr; \
1118 lr = aarch64_return_addr_rtx (); \
1119 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
1120 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \
1121 }
1122
1123 /* All the work done in PROFILE_HOOK, but still required. */
1124 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
1125
1126 /* For some reason, the Linux headers think they know how to define
1127 these macros. They don't!!! */
1128 #undef ASM_APP_ON
1129 #undef ASM_APP_OFF
1130 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n"
1131 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n"
1132
1133 #define CONSTANT_POOL_BEFORE_FUNCTION 0
1134
1135 /* This definition should be relocated to aarch64-elf-raw.h. This macro
1136 should be undefined in aarch64-linux.h and a clear_cache pattern
1137 implmented to emit either the call to __aarch64_sync_cache_range()
1138 directly or preferably the appropriate sycall or cache clear
1139 instructions inline. */
1140 #define CLEAR_INSN_CACHE(beg, end) \
1141 extern void __aarch64_sync_cache_range (void *, void *); \
1142 __aarch64_sync_cache_range (beg, end)
1143
1144 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
1145
1146 /* Choose appropriate mode for caller saves, so we do the minimum
1147 required size of load/store. */
1148 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1149 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
1150
1151 #undef SWITCHABLE_TARGET
1152 #define SWITCHABLE_TARGET 1
1153
1154 /* Check TLS Descriptors mechanism is selected. */
1155 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
1156
1157 extern enum aarch64_code_model aarch64_cmodel;
1158
1159 /* When using the tiny addressing model conditional and unconditional branches
1160 can span the whole of the available address space (1MB). */
1161 #define HAS_LONG_COND_BRANCH \
1162 (aarch64_cmodel == AARCH64_CMODEL_TINY \
1163 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1164
1165 #define HAS_LONG_UNCOND_BRANCH \
1166 (aarch64_cmodel == AARCH64_CMODEL_TINY \
1167 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1168
1169 #define TARGET_SUPPORTS_WIDE_INT 1
1170
1171 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */
1172 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
1173 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1174 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
1175 || (MODE) == DFmode || (MODE) == V4BFmode)
1176
1177 /* Modes valid for AdvSIMD Q registers. */
1178 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
1179 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1180 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
1181 || (MODE) == V2DFmode || (MODE) == V8BFmode)
1182
1183 #define ENDIAN_LANE_N(NUNITS, N) \
1184 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
1185
1186 /* Extra specs when building a native AArch64-hosted compiler.
1187 Option rewriting rules based on host system. */
1188 #if defined(__aarch64__)
1189 extern const char *host_detect_local_cpu (int argc, const char **argv);
1190 #define HAVE_LOCAL_CPU_DETECT
1191 # define EXTRA_SPEC_FUNCTIONS \
1192 { "local_cpu_detect", host_detect_local_cpu }, \
1193 MCPU_TO_MARCH_SPEC_FUNCTIONS
1194
1195 /* Rewrite -m{arch,cpu,tune}=native based on the host system information.
1196 When rewriting -march=native convert it into an -mcpu option if no other
1197 -mcpu or -mtune was given. */
1198 # define MCPU_MTUNE_NATIVE_SPECS \
1199 " %{march=native:%<march=native %:local_cpu_detect(%{mcpu=*|mtune=*:arch;:cpu})}" \
1200 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
1201 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
1202 /* This will be used in OPTION_DEFAULT_SPECS below.
1203 When GCC is configured with --with-tune we don't want to materialize an
1204 implicit -mtune would prevent the rewriting of -march=native into
1205 -mcpu=native as per the above rules. */
1206 #define CONFIG_TUNE_SPEC \
1207 { "tune", "%{!mcpu=*:%{!mtune=*:%{!march=native:-mtune=%(VALUE)}}}" },
1208 #else
1209 # define MCPU_MTUNE_NATIVE_SPECS ""
1210 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
1211 # define CONFIG_TUNE_SPEC \
1212 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"},
1213 #endif
1214
1215 /* Support for configure-time --with-arch, --with-cpu and --with-tune.
1216 --with-arch and --with-cpu are ignored if either -mcpu or -march is used.
1217 --with-tune is ignored if either -mtune or -mcpu is used (but is not
1218 affected by -march, except in the -march=native case as per the
1219 CONFIG_TUNE_SPEC above). */
1220 #define OPTION_DEFAULT_SPECS \
1221 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
1222 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
1223 CONFIG_TUNE_SPEC
1224
1225 #define MCPU_TO_MARCH_SPEC \
1226 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
1227
1228 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
1229 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
1230 { "rewrite_mcpu", aarch64_rewrite_mcpu },
1231
1232 #define ASM_CPU_SPEC \
1233 MCPU_TO_MARCH_SPEC
1234
1235 #define EXTRA_SPECS \
1236 { "asm_cpu_spec", ASM_CPU_SPEC }
1237
1238 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue
1239
1240 /* This type is the user-visible __fp16, and a pointer to that type. We
1241 need it in many places in the backend. Defined in aarch64-builtins.cc. */
1242 extern GTY(()) tree aarch64_fp16_type_node;
1243 extern GTY(()) tree aarch64_fp16_ptr_type_node;
1244
1245 /* Pointer to the user-visible __bf16 type. __bf16 itself is generic
1246 bfloat16_type_node. Defined in aarch64-builtins.cc. */
1247 extern GTY(()) tree aarch64_bf16_ptr_type_node;
1248
1249 /* The generic unwind code in libgcc does not initialize the frame pointer.
1250 So in order to unwind a function using a frame pointer, the very first
1251 function that is unwound must save the frame pointer. That way the frame
1252 pointer is restored and its value is now valid - otherwise _Unwind_GetGR
1253 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */
1254 #define LIBGCC2_UNWIND_ATTRIBUTE \
1255 __attribute__((optimize ("no-omit-frame-pointer")))
1256
1257 #ifndef USED_FOR_TARGET
1258 extern poly_uint16 aarch64_sve_vg;
1259
1260 /* The number of bits and bytes in an SVE vector. */
1261 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64))
1262 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8))
1263
1264 /* The number of bits and bytes in an SVE predicate. */
1265 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR
1266 #define BYTES_PER_SVE_PRED aarch64_sve_vg
1267
1268 /* The SVE mode for a vector of bytes. */
1269 #define SVE_BYTE_MODE VNx16QImode
1270
1271 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes
1272 (for -msve-vector-bits=2048) multiplied by the maximum number of
1273 vectors in a structure mode (4).
1274
1275 This limit must not be used for variable-size vectors, since
1276 VL-agnostic code must work with arbitary vector lengths. */
1277 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
1278 #endif
1279
1280 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE)
1281
1282 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the
1283 outgoing arguments if stack clash protection is enabled. This is essential
1284 as the extra arg space allows us to skip a check in alloca. */
1285 #undef STACK_DYNAMIC_OFFSET
1286 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1287 ((flag_stack_clash_protection \
1288 && cfun->calls_alloca \
1289 && known_lt (crtl->outgoing_args_size, \
1290 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \
1291 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \
1292 STACK_BOUNDARY / BITS_PER_UNIT) \
1293 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
1294
1295 #endif /* GCC_AARCH64_H */