1 /* NDS32-specific support for 32-bit ELF.
2 Copyright (C) 2012-2023 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22
23 #ifndef NDS32_ASM_H
24 #define NDS32_ASM_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 /* Constant values for assembler. */
31 enum
32 {
33 /* Error code for assembling an instruction. */
34 NASM_OK = 0,
35 NASM_ERR_UNKNOWN_OP,
36 NASM_ERR_SYNTAX,
37 NASM_ERR_OPERAND,
38 NASM_ERR_OUT_OF_RANGE,
39 NASM_ERR_REG_REDUCED,
40 NASM_ERR_JUNK_EOL,
41
42 /* Results of parse_operand. */
43 NASM_R_CONST,
44 NASM_R_SYMBOL,
45 NASM_R_ILLEGAL,
46
47 /* Flags for open description. */
48 NASM_OPEN_ARCH_V1 = 0x0,
49 NASM_OPEN_ARCH_V2 = 0x1,
50 NASM_OPEN_ARCH_V3 = 0x2,
51 NASM_OPEN_ARCH_V3M = 0x3,
52 NASM_OPEN_ARCH_MASK = 0xf,
53 NASM_OPEN_REDUCED_REG = 0x10,
54
55 /* Common attributes. */
56 NASM_ATTR_ISA_V1 = 0x01,
57 NASM_ATTR_ISA_V2 = 0x02,
58 NASM_ATTR_ISA_V3 = 0x04,
59 NASM_ATTR_ISA_V3M = 0x08,
60 NASM_ATTR_ISA_ALL = 0x0f,
61
62 /* Attributes for instructions. */
63 NASM_ATTR_MAC = 0x0000100,
64 NASM_ATTR_DIV = 0x0000200,
65 NASM_ATTR_FPU = 0x0000400,
66 NASM_ATTR_FPU_SP_EXT = 0x0000800,
67 NASM_ATTR_FPU_DP_EXT = 0x0001000,
68 NASM_ATTR_STR_EXT = 0x0002000,
69 NASM_ATTR_PERF_EXT = 0x0004000,
70 NASM_ATTR_PERF2_EXT = 0x0008000,
71 NASM_ATTR_AUDIO_ISAEXT = 0x0010000,
72 NASM_ATTR_IFC_EXT = 0x0020000,
73 NASM_ATTR_EX9_EXT = 0x0040000,
74 NASM_ATTR_FPU_FMA = 0x0080000,
75 NASM_ATTR_DXREG = 0x0100000,
76 NASM_ATTR_BRANCH = 0x0200000,
77 NASM_ATTR_SATURATION_EXT = 0x0400000,
78 NASM_ATTR_PCREL = 0x0800000,
79 NASM_ATTR_GPREL = 0x1000000,
80 NASM_ATTR_DSP_ISAEXT = 0x2000000,
81 NASM_ATTR_ZOL = (1 << 26),
82
83 /* Attributes for relocations. */
84 NASM_ATTR_HI20 = 0x10000000,
85 NASM_ATTR_LO12 = 0x20000000,
86 NASM_ATTR_LO20 = 0x40000000,
87
88 /* Attributes for registers. */
89 NASM_ATTR_RDREG = 0x000100
90 };
91
92 /* We only support one core for now. */
93 #define NDS32_CORE_COUNT 1
94 #define NDS32_MAIN_CORE 0
95
96 enum
97 {
98 /* This operand is used for input or output. (define or use) */
99 SYN_INPUT = 0x10000,
100 SYN_OUTPUT = 0x20000,
101 SYN_LOPT = 0x40000,
102 SYN_ROPT = 0x80000,
103
104 /* Hardware resources:
105 Current set up allows up to 256 resources for each class
106 defined above. */
107 HW_GPR = NDS32_MAIN_CORE << 8,
108 HW_USR,
109 HW_DXR,
110 HW_SR,
111 HW_FSR,
112 HW_FDR,
113 HW_CP, /* Co-processor ID. */
114 HW_CPR, /* Co-processor registers. */
115 HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */
116 HW_ABM, /* [ab]m? flag for LSMWZB. */
117 HW_DTITON,
118 HW_DTITOFF,
119 HW_DPREF_ST,
120 HW_CCTL_ST0,
121 HW_CCTL_ST1,
122 HW_CCTL_ST2,
123 HW_CCTL_ST3,
124 HW_CCTL_ST4,
125 HW_CCTL_ST5,
126 HW_CCTL_LV,
127 HW_TLBOP_ST,
128 HW_STANDBY_ST,
129 HW_MSYNC_ST,
130 HW_AEXT_IM_I,
131 HW_AEXT_IM_M,
132 HW_AEXT_ACC,
133 HW_AEXT_ARIDX,
134 HW_AEXT_ARIDX2,
135 HW_AEXT_ARIDXI,
136 HW_AEXT_ARIDXI_MX,
137 _HW_LAST,
138 HW_INT = 0x1000,
139 HW_UINT
140 };
141
142 /* for audio-extension. */
143 enum
144 {
145 N32_AEXT_AMADD = 0,
146 N32_AEXT_AMSUB,
147 N32_AEXT_AMULT,
148 N32_AEXT_AMFAR,
149 N32_AEXT_AMADDS,
150 N32_AEXT_AMSUBS,
151 N32_AEXT_AMULTS,
152 N32_AEXT_AMNEGS,
153 N32_AEXT_AADDL,
154 N32_AEXT_AMTARI,
155 N32_AEXT_AMAWBS = 0x0c,
156 N32_AEXT_AMAWTS,
157 N32_AEXT_AMWBS,
158 N32_AEXT_AMWTS,
159 N32_AEXT_AMABBS,
160 N32_AEXT_AMABTS,
161 N32_AEXT_AMATBS,
162 N32_AEXT_AMATTS,
163 N32_AEXT_AMBBS,
164 N32_AEXT_AMBTS,
165 N32_AEXT_AMTBS,
166 N32_AEXT_AMTTS
167 };
168
169 /* Macro for instruction attribute. */
170 #define ATTR(attr) NASM_ATTR_ ## attr
171 #define ATTR_NONE 0
172 #define ATTR_PCREL (ATTR (PCREL) | ATTR (BRANCH))
173
174 #define ATTR_ALL (ATTR (ISA_ALL))
175 #define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1)))
176 #define ATTR_V3MUP (ATTR (ISA_V3) | ATTR (ISA_V3M))
177 #define ATTR_V3 (ATTR (ISA_V3))
178 #define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M)))
179 #define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M)))
180
181 /* Lexical element in parsed syntax. */
182 typedef int lex_t;
183
184 /* Common header for hash entries. */
185 struct nds32_hash_entry
186 {
187 const char *name;
188 };
189
190 typedef struct nds32_keyword
191 {
192 const char *name;
193 int value;
194 uint64_t attr;
195 } keyword_t;
196
197 typedef struct nds32_opcode
198 {
199 /* Opcode for the instruction. */
200 const char *opcode;
201 /* Human readable string of this instruction. */
202 const char *instruction;
203 /* Base value of this instruction. */
204 uint32_t value;
205 /* The byte-size of the instruction. */
206 int isize;
207 /* Attributes of this instruction. */
208 uint64_t attr;
209 /* Implicit define/use. */
210 uint64_t defuse;
211 /* Parsed string for assembling. */
212 lex_t *syntax;
213 /* Number of variant. */
214 int variant;
215 /* Next form of the same mnemonic. */
216 struct nds32_opcode *next;
217
218 /* TODO: Extra constrains and verification.
219 For example, `mov55 $sp, $sp' is not allowed in v3. */
220 } opcode_t;
221
222 typedef struct nds32_asm_insn
223 {
224 /* Assembled instruction bytes. */
225 uint32_t insn;
226 /* The opcode structure for this instruction. */
227 struct nds32_opcode *opcode;
228 /* The field need special fix-up, used for relocation. */
229 const struct nds32_field *field;
230 /* Attributes for relocation. */
231 uint64_t attr;
232 /* Application-dependent data, e.g., expression. */
233 void *info;
234 /* Input/output registers. */
235 uint64_t defuse;
236 } nds32_asm_insn_t;
237
238 typedef struct nds32_asm_desc
239 {
240 /* The callback provided by assembler user for parse an operand,
241 e.g., parse integer. */
242 int (*parse_operand) (struct nds32_asm_desc *,
243 struct nds32_asm_insn *,
244 char **, int64_t *);
245
246 /* Result of assembling. */
247 int result;
248
249 /* The mach for this assembling. */
250 int mach;
251
252 int flags;
253 } nds32_asm_desc_t;
254
255 /* The field information for an operand. */
256 typedef struct nds32_field
257 {
258 /* Name of the field. */
259 const char *name;
260
261 int bitpos;
262 int bitsize;
263 int shift;
264 int hw_res;
265
266 int (*parse) (struct nds32_asm_desc *,
267 struct nds32_asm_insn *,
268 char **, int64_t *);
269 } field_t;
270
271 extern const field_t *nds32_field_table[NDS32_CORE_COUNT];
272 extern opcode_t *nds32_opcode_table[NDS32_CORE_COUNT];
273 extern const keyword_t **nds32_keyword_table[NDS32_CORE_COUNT];
274 extern struct nds32_opcode nds32_opcodes[];
275 extern const field_t nds32_operand_fields[];
276 extern const keyword_t *nds32_keywords[];
277 extern const keyword_t nds32_keyword_gpr[];
278
279 extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *);
280 extern void nds32_asm_init (nds32_asm_desc_t *, int);
281
282 #define OP6(op6) (N32_OP6_ ## op6 << 25)
283
284 #define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub)
285 #define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub)
286 #define JREG_RET (1 << 5)
287 #define JREG_IFC (1 << 6)
288 #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
289 #define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub)
290 #define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub)
291 #define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub)
292 #define ALU2_1(sub) (OP6 (ALU2) | N32_BIT (6) | N32_ALU2_ ## sub)
293 #define ALU2_2(sub) (OP6 (ALU2) | N32_BIT (7) | N32_ALU2_ ## sub)
294 #define ALU2_3(sub) (OP6 (ALU2) | N32_BIT (6) | N32_BIT (7) | N32_ALU2_ ## sub)
295 #define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
296 #define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
297 #define FPU_RA_IMMBI(sub) (OP6 (sub) | N32_BIT (12))
298 #define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
299 #define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
300 | (N32_FPU_FS1_F2OP_ ## sub << 10))
301 #define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
302 #define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
303 #define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
304 | (N32_FPU_FD1_F2OP_ ## sub << 10))
305 #define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
306 #define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
307 #define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
308 | (N32_FPU_MFCP_XR_ ## sub << 10))
309 #define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
310 #define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
311 | (N32_FPU_MTCP_XR_ ## sub << 10))
312 #define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub)
313 #define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7)
314 #define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20))
315
316 #ifdef __cplusplus
317 }
318 #endif
319
320 #endif