1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2023 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 #include "opcode/i386.h"
22 #include <limits.h>
23 #ifndef CHAR_BIT
24 #define CHAR_BIT 8
25 #endif
26
27 /* Position of cpu flags bitfiled. */
28
29 enum
30 {
31 /* i186 or better required */
32 Cpu186 = 0,
33 /* i286 or better required */
34 Cpu286,
35 /* i386 or better required */
36 Cpu386,
37 /* i486 or better required */
38 Cpu486,
39 /* i585 or better required */
40 Cpu586,
41 /* i686 or better required */
42 Cpu686,
43 /* CMOV Instruction support required */
44 CpuCMOV,
45 /* FXSR Instruction support required */
46 CpuFXSR,
47 /* CLFLUSH Instruction support required */
48 CpuClflush,
49 /* NOP Instruction support required */
50 CpuNop,
51 /* SYSCALL Instructions support required */
52 CpuSYSCALL,
53 /* Floating point support required */
54 Cpu8087,
55 /* i287 support required */
56 Cpu287,
57 /* i387 support required */
58 Cpu387,
59 /* i686 and floating point support required */
60 Cpu687,
61 /* SSE3 and floating point support required */
62 CpuFISTTP,
63 /* MMX support required */
64 CpuMMX,
65 /* SSE support required */
66 CpuSSE,
67 /* SSE2 support required */
68 CpuSSE2,
69 /* 3dnow! support required */
70 Cpu3dnow,
71 /* 3dnow! Extensions support required */
72 Cpu3dnowA,
73 /* SSE3 support required */
74 CpuSSE3,
75 /* VIA PadLock required */
76 CpuPadLock,
77 /* AMD Secure Virtual Machine Ext-s required */
78 CpuSVME,
79 /* VMX Instructions required */
80 CpuVMX,
81 /* SMX Instructions required */
82 CpuSMX,
83 /* SSSE3 support required */
84 CpuSSSE3,
85 /* SSE4a support required */
86 CpuSSE4a,
87 /* LZCNT support required */
88 CpuLZCNT,
89 /* POPCNT support required */
90 CpuPOPCNT,
91 /* MONITOR support required */
92 CpuMONITOR,
93 /* SSE4.1 support required */
94 CpuSSE4_1,
95 /* SSE4.2 support required */
96 CpuSSE4_2,
97 /* AVX support required */
98 CpuAVX,
99 /* AVX2 support required */
100 CpuAVX2,
101 /* Intel AVX-512 Foundation Instructions support required */
102 CpuAVX512F,
103 /* Intel AVX-512 Conflict Detection Instructions support required */
104 CpuAVX512CD,
105 /* Intel AVX-512 Exponential and Reciprocal Instructions support
106 required */
107 CpuAVX512ER,
108 /* Intel AVX-512 Prefetch Instructions support required */
109 CpuAVX512PF,
110 /* Intel AVX-512 VL Instructions support required. */
111 CpuAVX512VL,
112 /* Intel AVX-512 DQ Instructions support required. */
113 CpuAVX512DQ,
114 /* Intel AVX-512 BW Instructions support required. */
115 CpuAVX512BW,
116 /* Intel IAMCU support required */
117 CpuIAMCU,
118 /* Xsave/xrstor New Instructions support required */
119 CpuXsave,
120 /* Xsaveopt New Instructions support required */
121 CpuXsaveopt,
122 /* AES support required */
123 CpuAES,
124 /* PCLMUL support required */
125 CpuPCLMUL,
126 /* FMA support required */
127 CpuFMA,
128 /* FMA4 support required */
129 CpuFMA4,
130 /* XOP support required */
131 CpuXOP,
132 /* LWP support required */
133 CpuLWP,
134 /* BMI support required */
135 CpuBMI,
136 /* TBM support required */
137 CpuTBM,
138 /* MOVBE Instruction support required */
139 CpuMovbe,
140 /* CMPXCHG16B instruction support required. */
141 CpuCX16,
142 /* LAHF/SAHF instruction support required (in 64-bit mode). */
143 CpuLAHF_SAHF,
144 /* EPT Instructions required */
145 CpuEPT,
146 /* RDTSCP Instruction support required */
147 CpuRdtscp,
148 /* FSGSBASE Instructions required */
149 CpuFSGSBase,
150 /* RDRND Instructions required */
151 CpuRdRnd,
152 /* F16C Instructions required */
153 CpuF16C,
154 /* Intel BMI2 support required */
155 CpuBMI2,
156 /* HLE support required */
157 CpuHLE,
158 /* RTM support required */
159 CpuRTM,
160 /* INVPCID Instructions required */
161 CpuINVPCID,
162 /* VMFUNC Instruction required */
163 CpuVMFUNC,
164 /* Intel MPX Instructions required */
165 CpuMPX,
166 /* 64bit support available, used by -march= in assembler. */
167 CpuLM,
168 /* RDRSEED instruction required. */
169 CpuRDSEED,
170 /* Multi-presisionn add-carry instructions are required. */
171 CpuADX,
172 /* Supports prefetchw and prefetch instructions. */
173 CpuPRFCHW,
174 /* SMAP instructions required. */
175 CpuSMAP,
176 /* SHA instructions required. */
177 CpuSHA,
178 /* CLFLUSHOPT instruction required */
179 CpuClflushOpt,
180 /* XSAVES/XRSTORS instruction required */
181 CpuXSAVES,
182 /* XSAVEC instruction required */
183 CpuXSAVEC,
184 /* PREFETCHWT1 instruction required */
185 CpuPREFETCHWT1,
186 /* SE1 instruction required */
187 CpuSE1,
188 /* CLWB instruction required */
189 CpuCLWB,
190 /* Intel AVX-512 IFMA Instructions support required. */
191 CpuAVX512IFMA,
192 /* Intel AVX-512 VBMI Instructions support required. */
193 CpuAVX512VBMI,
194 /* Intel AVX-512 4FMAPS Instructions support required. */
195 CpuAVX512_4FMAPS,
196 /* Intel AVX-512 4VNNIW Instructions support required. */
197 CpuAVX512_4VNNIW,
198 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
199 CpuAVX512_VPOPCNTDQ,
200 /* Intel AVX-512 VBMI2 Instructions support required. */
201 CpuAVX512_VBMI2,
202 /* Intel AVX-512 VNNI Instructions support required. */
203 CpuAVX512_VNNI,
204 /* Intel AVX-512 BITALG Instructions support required. */
205 CpuAVX512_BITALG,
206 /* Intel AVX-512 BF16 Instructions support required. */
207 CpuAVX512_BF16,
208 /* Intel AVX-512 VP2INTERSECT Instructions support required. */
209 CpuAVX512_VP2INTERSECT,
210 /* TDX Instructions support required. */
211 CpuTDX,
212 /* Intel AVX VNNI Instructions support required. */
213 CpuAVX_VNNI,
214 /* Intel AVX-512 FP16 Instructions support required. */
215 CpuAVX512_FP16,
216 /* PREFETCHI instruction required */
217 CpuPREFETCHI,
218 /* Intel AVX IFMA Instructions support required. */
219 CpuAVX_IFMA,
220 /* Intel AVX VNNI-INT8 Instructions support required. */
221 CpuAVX_VNNI_INT8,
222 /* Intel CMPccXADD instructions support required. */
223 CpuCMPCCXADD,
224 /* Intel WRMSRNS Instructions support required */
225 CpuWRMSRNS,
226 /* Intel MSRLIST Instructions support required. */
227 CpuMSRLIST,
228 /* Intel AVX NE CONVERT Instructions support required. */
229 CpuAVX_NE_CONVERT,
230 /* Intel RAO INT Instructions support required. */
231 CpuRAO_INT,
232 /* fred instruction required */
233 CpuFRED,
234 /* lkgs instruction required */
235 CpuLKGS,
236 /* mwaitx instruction required */
237 CpuMWAITX,
238 /* Clzero instruction required */
239 CpuCLZERO,
240 /* OSPKE instruction required */
241 CpuOSPKE,
242 /* RDPID instruction required */
243 CpuRDPID,
244 /* PTWRITE instruction required */
245 CpuPTWRITE,
246 /* CET instructions support required */
247 CpuIBT,
248 CpuSHSTK,
249 /* AMX-INT8 instructions required */
250 CpuAMX_INT8,
251 /* AMX-BF16 instructions required */
252 CpuAMX_BF16,
253 /* AMX-FP16 instructions required */
254 CpuAMX_FP16,
255 /* AMX-COMPLEX instructions required. */
256 CpuAMX_COMPLEX,
257 /* AMX-TILE instructions required */
258 CpuAMX_TILE,
259 /* GFNI instructions required */
260 CpuGFNI,
261 /* VAES instructions required */
262 CpuVAES,
263 /* VPCLMULQDQ instructions required */
264 CpuVPCLMULQDQ,
265 /* WBNOINVD instructions required */
266 CpuWBNOINVD,
267 /* PCONFIG instructions required */
268 CpuPCONFIG,
269 /* WAITPKG instructions required */
270 CpuWAITPKG,
271 /* UINTR instructions required */
272 CpuUINTR,
273 /* CLDEMOTE instruction required */
274 CpuCLDEMOTE,
275 /* MOVDIRI instruction support required */
276 CpuMOVDIRI,
277 /* MOVDIRR64B instruction required */
278 CpuMOVDIR64B,
279 /* ENQCMD instruction required */
280 CpuENQCMD,
281 /* SERIALIZE instruction required */
282 CpuSERIALIZE,
283 /* RDPRU instruction required */
284 CpuRDPRU,
285 /* MCOMMIT instruction required */
286 CpuMCOMMIT,
287 /* SEV-ES instruction(s) required */
288 CpuSEV_ES,
289 /* TSXLDTRK instruction required */
290 CpuTSXLDTRK,
291 /* KL instruction support required */
292 CpuKL,
293 /* WideKL instruction support required */
294 CpuWideKL,
295 /* HRESET instruction required */
296 CpuHRESET,
297 /* INVLPGB instructions required */
298 CpuINVLPGB,
299 /* TLBSYNC instructions required */
300 CpuTLBSYNC,
301 /* SNP instructions required */
302 CpuSNP,
303 /* RMPQUERY instruction required */
304 CpuRMPQUERY,
305
306 /* NOTE: These last three items need to remain last and in this order. */
307
308 /* 64bit support required */
309 Cpu64,
310 /* Not supported in the 64bit mode */
311 CpuNo64,
312 /* The last bitfield in i386_cpu_flags. */
313 CpuMax = CpuNo64
314 };
315
316 #define CpuNumOfUints \
317 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
318 #define CpuNumOfBits \
319 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
320
321 /* If you get a compiler error for zero width of the unused field,
322 comment it out. */
323 #define CpuUnused (CpuMax + 1)
324
325 /* We can check if an instruction is available with array instead
326 of bitfield. */
327 typedef union i386_cpu_flags
328 {
329 struct
330 {
331 unsigned int cpui186:1;
332 unsigned int cpui286:1;
333 unsigned int cpui386:1;
334 unsigned int cpui486:1;
335 unsigned int cpui586:1;
336 unsigned int cpui686:1;
337 unsigned int cpucmov:1;
338 unsigned int cpufxsr:1;
339 unsigned int cpuclflush:1;
340 unsigned int cpunop:1;
341 unsigned int cpusyscall:1;
342 unsigned int cpu8087:1;
343 unsigned int cpu287:1;
344 unsigned int cpu387:1;
345 unsigned int cpu687:1;
346 unsigned int cpufisttp:1;
347 unsigned int cpummx:1;
348 unsigned int cpusse:1;
349 unsigned int cpusse2:1;
350 unsigned int cpua3dnow:1;
351 unsigned int cpua3dnowa:1;
352 unsigned int cpusse3:1;
353 unsigned int cpupadlock:1;
354 unsigned int cpusvme:1;
355 unsigned int cpuvmx:1;
356 unsigned int cpusmx:1;
357 unsigned int cpussse3:1;
358 unsigned int cpusse4a:1;
359 unsigned int cpulzcnt:1;
360 unsigned int cpupopcnt:1;
361 unsigned int cpumonitor:1;
362 unsigned int cpusse4_1:1;
363 unsigned int cpusse4_2:1;
364 unsigned int cpuavx:1;
365 unsigned int cpuavx2:1;
366 unsigned int cpuavx512f:1;
367 unsigned int cpuavx512cd:1;
368 unsigned int cpuavx512er:1;
369 unsigned int cpuavx512pf:1;
370 unsigned int cpuavx512vl:1;
371 unsigned int cpuavx512dq:1;
372 unsigned int cpuavx512bw:1;
373 unsigned int cpuiamcu:1;
374 unsigned int cpuxsave:1;
375 unsigned int cpuxsaveopt:1;
376 unsigned int cpuaes:1;
377 unsigned int cpupclmul:1;
378 unsigned int cpufma:1;
379 unsigned int cpufma4:1;
380 unsigned int cpuxop:1;
381 unsigned int cpulwp:1;
382 unsigned int cpubmi:1;
383 unsigned int cputbm:1;
384 unsigned int cpumovbe:1;
385 unsigned int cpucx16:1;
386 unsigned int cpulahf_sahf:1;
387 unsigned int cpuept:1;
388 unsigned int cpurdtscp:1;
389 unsigned int cpufsgsbase:1;
390 unsigned int cpurdrnd:1;
391 unsigned int cpuf16c:1;
392 unsigned int cpubmi2:1;
393 unsigned int cpuhle:1;
394 unsigned int cpurtm:1;
395 unsigned int cpuinvpcid:1;
396 unsigned int cpuvmfunc:1;
397 unsigned int cpumpx:1;
398 unsigned int cpulm:1;
399 unsigned int cpurdseed:1;
400 unsigned int cpuadx:1;
401 unsigned int cpuprfchw:1;
402 unsigned int cpusmap:1;
403 unsigned int cpusha:1;
404 unsigned int cpuclflushopt:1;
405 unsigned int cpuxsaves:1;
406 unsigned int cpuxsavec:1;
407 unsigned int cpuprefetchwt1:1;
408 unsigned int cpuse1:1;
409 unsigned int cpuclwb:1;
410 unsigned int cpuavx512ifma:1;
411 unsigned int cpuavx512vbmi:1;
412 unsigned int cpuavx512_4fmaps:1;
413 unsigned int cpuavx512_4vnniw:1;
414 unsigned int cpuavx512_vpopcntdq:1;
415 unsigned int cpuavx512_vbmi2:1;
416 unsigned int cpuavx512_vnni:1;
417 unsigned int cpuavx512_bitalg:1;
418 unsigned int cpuavx512_bf16:1;
419 unsigned int cpuavx512_vp2intersect:1;
420 unsigned int cputdx:1;
421 unsigned int cpuavx_vnni:1;
422 unsigned int cpuavx512_fp16:1;
423 unsigned int cpuprefetchi:1;
424 unsigned int cpuavx_ifma:1;
425 unsigned int cpuavx_vnni_int8:1;
426 unsigned int cpucmpccxadd:1;
427 unsigned int cpuwrmsrns:1;
428 unsigned int cpumsrlist:1;
429 unsigned int cpuavx_ne_convert:1;
430 unsigned int cpurao_int:1;
431 unsigned int cpufred:1;
432 unsigned int cpulkgs:1;
433 unsigned int cpumwaitx:1;
434 unsigned int cpuclzero:1;
435 unsigned int cpuospke:1;
436 unsigned int cpurdpid:1;
437 unsigned int cpuptwrite:1;
438 unsigned int cpuibt:1;
439 unsigned int cpushstk:1;
440 unsigned int cpuamx_int8:1;
441 unsigned int cpuamx_bf16:1;
442 unsigned int cpuamx_fp16:1;
443 unsigned int cpuamx_complex:1;
444 unsigned int cpuamx_tile:1;
445 unsigned int cpugfni:1;
446 unsigned int cpuvaes:1;
447 unsigned int cpuvpclmulqdq:1;
448 unsigned int cpuwbnoinvd:1;
449 unsigned int cpupconfig:1;
450 unsigned int cpuwaitpkg:1;
451 unsigned int cpuuintr:1;
452 unsigned int cpucldemote:1;
453 unsigned int cpumovdiri:1;
454 unsigned int cpumovdir64b:1;
455 unsigned int cpuenqcmd:1;
456 unsigned int cpuserialize:1;
457 unsigned int cpurdpru:1;
458 unsigned int cpumcommit:1;
459 unsigned int cpusev_es:1;
460 unsigned int cputsxldtrk:1;
461 unsigned int cpukl:1;
462 unsigned int cpuwidekl:1;
463 unsigned int cpuhreset:1;
464 unsigned int cpuinvlpgb:1;
465 unsigned int cputlbsync:1;
466 unsigned int cpusnp:1;
467 unsigned int cpurmpquery:1;
468 /* NOTE: These last three fields need to remain last and in this order. */
469 unsigned int cpu64:1;
470 unsigned int cpuno64:1;
471 #ifdef CpuUnused
472 unsigned int unused:(CpuNumOfBits - CpuUnused);
473 #endif
474 } bitfield;
475 unsigned int array[CpuNumOfUints];
476 } i386_cpu_flags;
477
478 /* Position of opcode_modifier bits. */
479
480 enum
481 {
482 /* has direction bit. */
483 D = 0,
484 /* set if operands can be both bytes and words/dwords/qwords, encoded the
485 canonical way; the base_opcode field should hold the encoding for byte
486 operands */
487 W,
488 /* load form instruction. Must be placed before store form. */
489 Load,
490 /* insn has a modrm byte. */
491 Modrm,
492 /* special case for jump insns; value has to be 1 */
493 #define JUMP 1
494 /* call and jump */
495 #define JUMP_DWORD 2
496 /* loop and jecxz */
497 #define JUMP_BYTE 3
498 /* special case for intersegment leaps/calls */
499 #define JUMP_INTERSEGMENT 4
500 /* absolute address for jump */
501 #define JUMP_ABSOLUTE 5
502 Jump,
503 /* FP insn memory format bit, sized by 0x4 */
504 FloatMF,
505 /* needs size prefix if in 32-bit mode */
506 #define SIZE16 1
507 /* needs size prefix if in 16-bit mode */
508 #define SIZE32 2
509 /* needs size prefix if in 64-bit mode */
510 #define SIZE64 3
511 Size,
512 /* Check that operand sizes match. */
513 CheckOperandSize,
514 /* any memory size */
515 #define ANY_SIZE 1
516 /* fake an extra reg operand for clr, imul and special register
517 processing for some instructions. */
518 #define REG_KLUDGE 2
519 /* deprecated fp insn, gets a warning */
520 #define UGH 3
521 /* An implicit xmm0 as the first operand */
522 #define IMPLICIT_1ST_XMM0 4
523 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
524 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
525 */
526 #define IMPLICIT_QUAD_GROUP 5
527 /* Two source operands are swapped. */
528 #define SWAP_SOURCES 6
529 /* Default mask isn't allowed. */
530 #define NO_DEFAULT_MASK 7
531 /* Address prefix changes register operand */
532 #define ADDR_PREFIX_OP_REG 8
533 /* Instrucion requires that destination must be distinct from source
534 registers. */
535 #define DISTINCT_DEST 9
536 OperandConstraint,
537 /* instruction ignores operand size prefix and in Intel mode ignores
538 mnemonic size suffix check. */
539 #define IGNORESIZE 1
540 /* default insn size depends on mode */
541 #define DEFAULTSIZE 2
542 MnemonicSize,
543 /* b suffix on instruction illegal */
544 No_bSuf,
545 /* w suffix on instruction illegal */
546 No_wSuf,
547 /* l suffix on instruction illegal */
548 No_lSuf,
549 /* s suffix on instruction illegal */
550 No_sSuf,
551 /* q suffix on instruction illegal */
552 No_qSuf,
553 /* instruction needs FWAIT */
554 FWait,
555 /* IsString provides for a quick test for string instructions, and
556 its actual value also indicates which of the operands (if any)
557 requires use of the %es segment. */
558 #define IS_STRING_ES_OP0 2
559 #define IS_STRING_ES_OP1 3
560 IsString,
561 /* RegMem is for instructions with a modrm byte where the register
562 destination operand should be encoded in the mod and regmem fields.
563 Normally, it will be encoded in the reg field. We add a RegMem
564 flag to indicate that it should be encoded in the regmem field. */
565 RegMem,
566 /* quick test if branch instruction is MPX supported */
567 BNDPrefixOk,
568 #define PrefixNone 0
569 #define PrefixRep 1
570 #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */
571 #define PrefixNoTrack 3
572 /* Prefixes implying "LOCK okay" must come after Lock. All others have
573 to come before. */
574 #define PrefixLock 4
575 #define PrefixHLELock 5 /* Okay with a LOCK prefix. */
576 #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */
577 PrefixOk,
578 /* opcode is a prefix */
579 IsPrefix,
580 /* instruction has extension in 8 bit imm */
581 ImmExt,
582 /* instruction don't need Rex64 prefix. */
583 NoRex64,
584 /* insn has VEX prefix:
585 1: 128bit VEX prefix (or operand dependent).
586 2: 256bit VEX prefix.
587 3: Scalar VEX prefix.
588 */
589 #define VEX128 1
590 #define VEX256 2
591 #define VEXScalar 3
592 Vex,
593 /* How to encode VEX.vvvv:
594 0: VEX.vvvv must be 1111b.
595 1: VEX.vvvv encodes one of the register operands.
596 */
597 VexVVVV,
598 /* How the VEX.W bit is used:
599 0: Set by the REX.W bit.
600 1: VEX.W0. Should always be 0.
601 2: VEX.W1. Should always be 1.
602 3: VEX.WIG. The VEX.W bit is ignored.
603 */
604 #define VEXW0 1
605 #define VEXW1 2
606 #define VEXWIG 3
607 VexW,
608 /* Opcode prefix (values chosen to be usable directly in
609 VEX/XOP/EVEX pp fields):
610 0: None
611 1: Add 0x66 opcode prefix.
612 2: Add 0xf3 opcode prefix.
613 3: Add 0xf2 opcode prefix.
614 */
615 #define PREFIX_NONE 0
616 #define PREFIX_0X66 1
617 #define PREFIX_0XF3 2
618 #define PREFIX_0XF2 3
619 OpcodePrefix,
620 /* Instruction with a mandatory SIB byte:
621 1: 128bit vector register.
622 2: 256bit vector register.
623 3: 512bit vector register.
624 */
625 #define VECSIB128 1
626 #define VECSIB256 2
627 #define VECSIB512 3
628 #define SIBMEM 4
629 SIB,
630
631 /* SSE to AVX support required */
632 SSE2AVX,
633
634 /* insn has EVEX prefix:
635 1: 512bit EVEX prefix.
636 2: 128bit EVEX prefix.
637 3: 256bit EVEX prefix.
638 4: Length-ignored (LIG) EVEX prefix.
639 5: Length determined from actual operands.
640 6: L'L = 3 (reserved, .insn only)
641 */
642 #define EVEX512 1
643 #define EVEX128 2
644 #define EVEX256 3
645 #define EVEXLIG 4
646 #define EVEXDYN 5
647 #define EVEX_L3 6
648 EVex,
649
650 /* AVX512 masking support */
651 Masking,
652
653 /* AVX512 broadcast support. The number of bytes to broadcast is
654 1 << (Broadcast - 1):
655 1: Byte broadcast.
656 2: Word broadcast.
657 3: Dword broadcast.
658 4: Qword broadcast.
659 */
660 #define BYTE_BROADCAST 1
661 #define WORD_BROADCAST 2
662 #define DWORD_BROADCAST 3
663 #define QWORD_BROADCAST 4
664 Broadcast,
665
666 /* Static rounding control is supported. */
667 StaticRounding,
668
669 /* Supress All Exceptions is supported. */
670 SAE,
671
672 /* Compressed Disp8*N attribute. */
673 #define DISP8_SHIFT_VL 7
674 Disp8MemShift,
675
676 /* Support encoding optimization. */
677 Optimize,
678
679 /* AT&T mnemonic. */
680 ATTMnemonic,
681 /* AT&T syntax. */
682 ATTSyntax,
683 /* Intel syntax. */
684 IntelSyntax,
685 /* ISA64: Don't change the order without other code adjustments.
686 0: Common to AMD64 and Intel64.
687 1: AMD64.
688 2: Intel64.
689 3: Only in Intel64.
690 */
691 #define AMD64 1
692 #define INTEL64 2
693 #define INTEL64ONLY 3
694 ISA64,
695 /* The last bitfield in i386_opcode_modifier. */
696 Opcode_Modifier_Num
697 };
698
699 typedef struct i386_opcode_modifier
700 {
701 unsigned int d:1;
702 unsigned int w:1;
703 unsigned int load:1;
704 unsigned int modrm:1;
705 unsigned int jump:3;
706 unsigned int floatmf:1;
707 unsigned int size:2;
708 unsigned int checkoperandsize:1;
709 unsigned int operandconstraint:4;
710 unsigned int mnemonicsize:2;
711 unsigned int no_bsuf:1;
712 unsigned int no_wsuf:1;
713 unsigned int no_lsuf:1;
714 unsigned int no_ssuf:1;
715 unsigned int no_qsuf:1;
716 unsigned int fwait:1;
717 unsigned int isstring:2;
718 unsigned int regmem:1;
719 unsigned int bndprefixok:1;
720 unsigned int prefixok:3;
721 unsigned int isprefix:1;
722 unsigned int immext:1;
723 unsigned int norex64:1;
724 unsigned int vex:2;
725 unsigned int vexvvvv:1;
726 unsigned int vexw:2;
727 unsigned int opcodeprefix:2;
728 unsigned int sib:3;
729 unsigned int sse2avx:1;
730 unsigned int evex:3;
731 unsigned int masking:1;
732 unsigned int broadcast:3;
733 unsigned int staticrounding:1;
734 unsigned int sae:1;
735 unsigned int disp8memshift:3;
736 unsigned int optimize:1;
737 unsigned int attmnemonic:1;
738 unsigned int attsyntax:1;
739 unsigned int intelsyntax:1;
740 unsigned int isa64:2;
741 } i386_opcode_modifier;
742
743 /* Operand classes. */
744
745 #define CLASS_WIDTH 4
746 enum operand_class
747 {
748 ClassNone,
749 Reg, /* GPRs and FP regs, distinguished by operand size */
750 SReg, /* Segment register */
751 RegCR, /* Control register */
752 RegDR, /* Debug register */
753 RegTR, /* Test register */
754 RegMMX, /* MMX register */
755 RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
756 RegMask, /* Vector Mask register */
757 RegBND, /* Bound register */
758 };
759
760 /* Special operand instances. */
761
762 #define INSTANCE_WIDTH 3
763 enum operand_instance
764 {
765 InstanceNone,
766 Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
767 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
768 RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
769 RegB, /* %bl / %bx / %ebx / %rbx */
770 };
771
772 /* Position of operand_type bits. */
773
774 enum
775 {
776 /* Class and Instance */
777 ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
778 /* 1 bit immediate */
779 Imm1,
780 /* 8 bit immediate */
781 Imm8,
782 /* 8 bit immediate sign extended */
783 Imm8S,
784 /* 16 bit immediate */
785 Imm16,
786 /* 32 bit immediate */
787 Imm32,
788 /* 32 bit immediate sign extended */
789 Imm32S,
790 /* 64 bit immediate */
791 Imm64,
792 /* 8bit/16bit/32bit displacements are used in different ways,
793 depending on the instruction. For jumps, they specify the
794 size of the PC relative displacement, for instructions with
795 memory operand, they specify the size of the offset relative
796 to the base register, and for instructions with memory offset
797 such as `mov 1234,%al' they specify the size of the offset
798 relative to the segment base. */
799 /* 8 bit displacement */
800 Disp8,
801 /* 16 bit displacement */
802 Disp16,
803 /* 32 bit displacement (64-bit: sign-extended) */
804 Disp32,
805 /* 64 bit displacement */
806 Disp64,
807 /* Register which can be used for base or index in memory operand. */
808 BaseIndex,
809 /* BYTE size. */
810 Byte,
811 /* WORD size. 2 byte */
812 Word,
813 /* DWORD size. 4 byte */
814 Dword,
815 /* FWORD size. 6 byte */
816 Fword,
817 /* QWORD size. 8 byte */
818 Qword,
819 /* TBYTE size. 10 byte */
820 Tbyte,
821 /* XMMWORD size. */
822 Xmmword,
823 /* YMMWORD size. */
824 Ymmword,
825 /* ZMMWORD size. */
826 Zmmword,
827 /* TMMWORD size. */
828 Tmmword,
829 /* Unspecified memory size. */
830 Unspecified,
831
832 /* The number of bits in i386_operand_type. */
833 OTNum
834 };
835
836 #define OTNumOfUints \
837 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
838 #define OTNumOfBits \
839 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
840
841 /* If you get a compiler error for zero width of the unused field,
842 comment it out. */
843 #define OTUnused OTNum
844
845 typedef union i386_operand_type
846 {
847 struct
848 {
849 unsigned int class:CLASS_WIDTH;
850 unsigned int instance:INSTANCE_WIDTH;
851 unsigned int imm1:1;
852 unsigned int imm8:1;
853 unsigned int imm8s:1;
854 unsigned int imm16:1;
855 unsigned int imm32:1;
856 unsigned int imm32s:1;
857 unsigned int imm64:1;
858 unsigned int disp8:1;
859 unsigned int disp16:1;
860 unsigned int disp32:1;
861 unsigned int disp64:1;
862 unsigned int baseindex:1;
863 unsigned int byte:1;
864 unsigned int word:1;
865 unsigned int dword:1;
866 unsigned int fword:1;
867 unsigned int qword:1;
868 unsigned int tbyte:1;
869 unsigned int xmmword:1;
870 unsigned int ymmword:1;
871 unsigned int zmmword:1;
872 unsigned int tmmword:1;
873 unsigned int unspecified:1;
874 #ifdef OTUnused
875 unsigned int unused:(OTNumOfBits - OTUnused);
876 #endif
877 } bitfield;
878 unsigned int array[OTNumOfUints];
879 } i386_operand_type;
880
881 typedef struct insn_template
882 {
883 /* instruction name sans width suffix ("mov" for movl insns) */
884 unsigned int mnem_off;
885
886 /* Bitfield arrangement is such that individual fields can be easily
887 extracted (in native builds at least) - either by at most a masking
888 operation (base_opcode, operands), or by just a (signed) right shift
889 (extension_opcode). Please try to maintain this property. */
890
891 /* base_opcode is the fundamental opcode byte without optional
892 prefix(es). */
893 unsigned int base_opcode:16;
894 #define Opcode_D 0x2 /* Direction bit:
895 set if Reg --> Regmem;
896 unset if Regmem --> Reg. */
897 #define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */
898 #define Opcode_FloatD 0x4 /* Direction bit for float insns. */
899 #define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */
900 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
901 /* The next value is arbitrary, as long as it's non-zero and distinct
902 from all other values above. */
903 #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */
904
905 /* how many operands */
906 unsigned int operands:3;
907
908 /* opcode space */
909 unsigned int opcode_space:4;
910 /* Opcode encoding space (values chosen to be usable directly in
911 VEX/XOP mmmmm and EVEX mm fields):
912 0: Base opcode space.
913 1: 0F opcode prefix / space.
914 2: 0F38 opcode prefix / space.
915 3: 0F3A opcode prefix / space.
916 5: EVEXMAP5 opcode prefix / space.
917 6: EVEXMAP6 opcode prefix / space.
918 8: XOP 08 opcode space.
919 9: XOP 09 opcode space.
920 A: XOP 0A opcode space.
921 */
922 #define SPACE_BASE 0
923 #define SPACE_0F 1
924 #define SPACE_0F38 2
925 #define SPACE_0F3A 3
926 #define SPACE_EVEXMAP5 5
927 #define SPACE_EVEXMAP6 6
928 #define SPACE_XOP08 8
929 #define SPACE_XOP09 9
930 #define SPACE_XOP0A 0xA
931
932 /* (Fake) base opcode value for pseudo prefixes. */
933 #define PSEUDO_PREFIX 0
934
935 /* extension_opcode is the 3 bit extension for group <n> insns.
936 This field is also used to store the 8-bit opcode suffix for the
937 AMD 3DNow! instructions.
938 If this template has no extension opcode (the usual case) use None
939 Instructions */
940 signed int extension_opcode:9;
941 #define None (-1) /* If no extension_opcode is possible. */
942
943 /* Pseudo prefixes. */
944 #define Prefix_Disp8 0 /* {disp8} */
945 #define Prefix_Disp16 1 /* {disp16} */
946 #define Prefix_Disp32 2 /* {disp32} */
947 #define Prefix_Load 3 /* {load} */
948 #define Prefix_Store 4 /* {store} */
949 #define Prefix_VEX 5 /* {vex} */
950 #define Prefix_VEX3 6 /* {vex3} */
951 #define Prefix_EVEX 7 /* {evex} */
952 #define Prefix_REX 8 /* {rex} */
953 #define Prefix_NoOptimize 9 /* {nooptimize} */
954
955 /* the bits in opcode_modifier are used to generate the final opcode from
956 the base_opcode. These bits also are used to detect alternate forms of
957 the same instruction */
958 i386_opcode_modifier opcode_modifier;
959
960 /* cpu feature flags */
961 i386_cpu_flags cpu_flags;
962
963 /* operand_types[i] describes the type of operand i. This is made
964 by OR'ing together all of the possible type masks. (e.g.
965 'operand_types[i] = Reg|Imm' specifies that operand i can be
966 either a register or an immediate operand. */
967 i386_operand_type operand_types[MAX_OPERANDS];
968 }
969 insn_template;
970
971 /* these are for register name --> number & type hash lookup */
972 typedef struct
973 {
974 char reg_name[8];
975 i386_operand_type reg_type;
976 unsigned char reg_flags;
977 #define RegRex 0x1 /* Extended register. */
978 #define RegRex64 0x2 /* Extended 8 bit register. */
979 #define RegVRex 0x4 /* Extended vector register. */
980 unsigned char reg_num;
981 #define RegIP ((unsigned char ) ~0)
982 /* EIZ and RIZ are fake index registers. */
983 #define RegIZ (RegIP - 1)
984 /* FLAT is a fake segment register (Intel mode). */
985 #define RegFlat ((unsigned char) ~0)
986 signed char dw2_regnum[2];
987 #define Dw2Inval (-1)
988 }
989 reg_entry;