1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* CPU data header for bpf.
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5
6 Copyright (C) 1996-2023 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24 */
25
26 #ifndef BPF_CPU_H
27 #define BPF_CPU_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #define CGEN_ARCH bpf
34
35 /* Given symbol S, return bpf_cgen_<S>. */
36 #define CGEN_SYM(s) bpf##_cgen_##s
37
38
39 /* Selected cpu families. */
40 #define HAVE_CPU_BPFBF
41
42 #define CGEN_INSN_LSB0_P 1
43
44 /* Minimum size of any insn (in bytes). */
45 #define CGEN_MIN_INSN_SIZE 8
46
47 /* Maximum size of any insn (in bytes). */
48 #define CGEN_MAX_INSN_SIZE 16
49
50 #define CGEN_INT_INSN_P 0
51
52 /* Maximum number of syntax elements in an instruction. */
53 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16
54
55 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
56 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
57 we can't hash on everything up to the space. */
58 #define CGEN_MNEMONIC_OPERANDS
59
60 /* Maximum number of fields in an instruction. */
61 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
62
63 /* Enums. */
64
65 /* Enum declaration for eBPF instruction codes. */
66 typedef enum insn_op_code_alu {
67 OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
68 , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
69 , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
70 , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_SDIV = 14, OP_CODE_SMOD = 15
71 , OP_CODE_JA = 0, OP_CODE_JEQ = 1, OP_CODE_JGT = 2, OP_CODE_JGE = 3
72 , OP_CODE_JSET = 4, OP_CODE_JNE = 5, OP_CODE_JSGT = 6, OP_CODE_JSGE = 7
73 , OP_CODE_CALL = 8, OP_CODE_EXIT = 9, OP_CODE_JLT = 10, OP_CODE_JLE = 11
74 , OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
75 } INSN_OP_CODE_ALU;
76
77 /* Enum declaration for eBPF instruction source. */
78 typedef enum insn_op_src {
79 OP_SRC_K, OP_SRC_X
80 } INSN_OP_SRC;
81
82 /* Enum declaration for eBPF instruction class. */
83 typedef enum insn_op_class {
84 OP_CLASS_LD, OP_CLASS_LDX, OP_CLASS_ST, OP_CLASS_STX
85 , OP_CLASS_ALU, OP_CLASS_JMP, OP_CLASS_JMP32, OP_CLASS_ALU64
86 } INSN_OP_CLASS;
87
88 /* Enum declaration for eBPF load/store instruction modes. */
89 typedef enum insn_op_mode {
90 OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3
91 , OP_MODE_XADD = 6
92 } INSN_OP_MODE;
93
94 /* Enum declaration for eBPF load/store instruction sizes. */
95 typedef enum insn_op_size {
96 OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW
97 } INSN_OP_SIZE;
98
99 /* Attributes. */
100
101 /* Enum declaration for machine type selection. */
102 typedef enum mach_attr {
103 MACH_BASE, MACH_BPF, MACH_XBPF, MACH_MAX
104 } MACH_ATTR;
105
106 /* Enum declaration for instruction set selection. */
107 typedef enum isa_attr {
108 ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE
109 , ISA_MAX
110 } ISA_ATTR;
111
112 /* Number of architecture variants. */
113 #define MAX_ISAS ((int) ISA_MAX)
114 #define MAX_MACHS ((int) MACH_MAX)
115
116 /* Ifield support. */
117
118 /* Ifield attribute indices. */
119
120 /* Enum declaration for cgen_ifld attrs. */
121 typedef enum cgen_ifld_attr {
122 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
123 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
124 , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
125 } CGEN_IFLD_ATTR;
126
127 /* Number of non-boolean elements in cgen_ifld_attr. */
128 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
129
130 /* cgen_ifld attribute accessor macros. */
131 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
132 #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
133 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
134 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
135 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
136 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
137 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
138 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
139
140 /* Enum declaration for bpf ifield types. */
141 typedef enum ifield_type {
142 BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC
143 , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE
144 , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS
145 , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B
146 , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX
147 } IFIELD_TYPE;
148
149 #define MAX_IFLD ((int) BPF_F_MAX)
150
151 /* Hardware attribute indices. */
152
153 /* Enum declaration for cgen_hw attrs. */
154 typedef enum cgen_hw_attr {
155 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
156 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
157 , CGEN_HW_END_NBOOLS
158 } CGEN_HW_ATTR;
159
160 /* Number of non-boolean elements in cgen_hw_attr. */
161 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
162
163 /* cgen_hw attribute accessor macros. */
164 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
165 #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
166 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
167 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
168 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
169 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
170
171 /* Enum declaration for bpf hardware types. */
172 typedef enum cgen_hw_type {
173 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
174 , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64
175 , HW_MAX
176 } CGEN_HW_TYPE;
177
178 #define MAX_HW ((int) HW_MAX)
179
180 /* Operand attribute indices. */
181
182 /* Enum declaration for cgen_operand attrs. */
183 typedef enum cgen_operand_attr {
184 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
185 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
186 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
187 , CGEN_OPERAND_END_NBOOLS
188 } CGEN_OPERAND_ATTR;
189
190 /* Number of non-boolean elements in cgen_operand_attr. */
191 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
192
193 /* cgen_operand attribute accessor macros. */
194 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
195 #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
196 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
197 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
198 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
199 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
200 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
201 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
202 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
203 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
204
205 /* Enum declaration for bpf operand types. */
206 typedef enum cgen_operand_type {
207 BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE
208 , BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32
209 , BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX
210 } CGEN_OPERAND_TYPE;
211
212 /* Number of operands types. */
213 #define MAX_OPERANDS 11
214
215 /* Maximum number of operands referenced by any insn. */
216 #define MAX_OPERAND_INSTANCES 8
217
218 /* Insn attribute indices. */
219
220 /* Enum declaration for cgen_insn attrs. */
221 typedef enum cgen_insn_attr {
222 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
223 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
224 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
225 , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS
226 } CGEN_INSN_ATTR;
227
228 /* Number of non-boolean elements in cgen_insn_attr. */
229 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
230
231 /* cgen_insn attribute accessor macros. */
232 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
233 #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
234 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
235 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
236 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
237 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
238 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
239 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
240 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
241 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
242 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
243 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
244
245 /* cgen.h uses things we just defined. */
246 #include "opcode/cgen.h"
247
248 extern const struct cgen_ifld bpf_cgen_ifld_table[];
249
250 /* Attributes. */
251 extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[];
252 extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[];
253 extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[];
254 extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[];
255
256 /* Hardware decls. */
257
258 extern CGEN_KEYWORD bpf_cgen_opval_h_gpr;
259
260 extern const CGEN_HW_ENTRY bpf_cgen_hw_table[];
261
262
263
264 #ifdef __cplusplus
265 }
266 #endif
267
268 #endif /* BPF_CPU_H */