1 /* ARC instruction defintions.
2 Copyright (C) 2016-2023 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 /* Common combinations of FLAGS. */
23 #define FLAGS_NONE { 0 }
24 #define FLAGS_F { C_F }
25 #define FLAGS_CC { C_CC }
26 #define FLAGS_CCF { C_CC, C_F }
27
28 /* Common combination of arguments. */
29 #define ARG_NONE { 0 }
30 #define ARG_32BIT_RARBRC { RA, RB, RC }
31 #define ARG_32BIT_ZARBRC { ZA, RB, RC }
32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
37 #define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
39 #define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
41
42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
43 #define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
44 #define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
45
46 #define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
47 #define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
48 #define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
49
50 #define ARG_32BIT_RBRC { RB, RC }
51 #define ARG_32BIT_ZARC { ZA, RC }
52 #define ARG_32BIT_RBU6 { RB, UIMM6_20 }
53 #define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
54 #define ARG_32BIT_RBLIMM { RB, LIMM }
55 #define ARG_32BIT_ZALIMM { ZA, LIMM }
56
57 /* Macro to generate 2 operand extension instruction. */
58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
59 { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
60 ARG_32BIT_RBRC, FL }, \
61 { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
62 ARG_32BIT_ZARC, FL }, \
63 { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
64 ARG_32BIT_RBU6, FL }, \
65 { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
66 ARG_32BIT_ZAU6, FL }, \
67 { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
68 ARG_32BIT_RBLIMM, FL }, \
69 { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
70 ARG_32BIT_ZALIMM, FL },
71
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
73 EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
74
75 /* Macro to generate 3 operand extesion instruction. */
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
77 { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
78 ARG_32BIT_RARBRC, FLAGS_F }, \
79 { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
80 ARG_32BIT_ZARBRC, FLAGS_F }, \
81 { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
82 ARG_32BIT_RBRBRC, FLAGS_CCF }, \
83 { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
84 ARG_32BIT_RARBU6, FLAGS_F }, \
85 { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
86 ARG_32BIT_ZARBU6, FLAGS_F }, \
87 { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
88 ARG_32BIT_RBRBU6, FLAGS_CCF }, \
89 { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
90 ARG_32BIT_RBRBS12, FLAGS_F }, \
91 { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
92 ARG_32BIT_RALIMMRC, FLAGS_F }, \
93 { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
94 ARG_32BIT_RARBLIMM, FLAGS_F }, \
95 { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
96 ARG_32BIT_ZALIMMRC, FLAGS_F }, \
97 { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
98 ARG_32BIT_ZARBLIMM, FLAGS_F }, \
99 { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
100 ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
101 { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
102 ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
103 { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
104 ARG_32BIT_RALIMMU6, FLAGS_F }, \
105 { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
106 ARG_32BIT_ZALIMMU6, FLAGS_F }, \
107 { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
108 ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
109 { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
110 ARG_32BIT_ZALIMMS12, FLAGS_F }, \
111 { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
112 ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
113 { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
114 ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
115 { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
116 ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
117
118 /* Extension instruction declarations. */
119 EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
120 EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
121 EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
122
123 EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
124 EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)